Back to results
US 6,191,412 B1Granted
Gain and error correction circuitry
AssigneeIntel Corporation
InventorMorteza Afghahi
Life of this patent
Estimating the term…
Abstract
Gain and error correction circuitry for metal-oxide-semiconductor (MOS) analog storage circuits, including image sensors. The correction circuitry allows the analog output signal for a storage cell to substantially track an input signal in each cell. Voltage dependent distortion and attenuation in the output signal, with respect to the input signal, is minimized, without significantly increasing the size of each cell.
Claims10
A circuit comprising:
- first portion having at least one first device receiving an input signal;
- second portion having at least one second device that is a replicate of the first device, the second portion being coupled to the first portion at an intermediate node;
- first control circuit for causing a first current through the second device;
- and
- second control circuit for causing a second current through the intermediate node,
- the second portion providing an output signal that is linearly proportional to the input signal in response to the first and second devices conducting the same amount of current.
3 more elements
A method comprising:
- applying an input signal to a first transistor to enable a first current through the transistor;
- controlling a second current through a second transistor that is a replicate of the first transistor, the second transistor being coupled to the first transistor so that the first and second currents are summed at an intermediate node;
- controlling a third current through the intermediate node, the third current being equal to twice the second current;
- and
- reading an output signal at an output of the second transistor.
2 more elements
Dependencies are inferred from the claim text.