US 6,191,047 B1 · Etching process using a buffer layer

Abstract

The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material. Where the buffer layer is of a conductive layer, the effect of the second etch is that the insulative layer is substantially undercut due to the etching of the buffer layer and due to selectivity to all other etch-exposed structures upon the semiconductor substrate. The undercut leaves a laterally-oriented second cavity within which lateral surfaces of the buffer layer are exposed. Following the second etch, a method of covering the laterally exposed surfaces of the buffer layer, exposed by the undercut, is chosen in order to isolate the remaining laterally exposed surfaces of the buffer layer. These methods include reflowing the insulative layer to cover the laterally exposed surfaces of the buffer layer, and forming a liner layer in the cavity to cover the laterally exposed surfaces of the buffer layer.

Claims36

Dependent claims

A fabrication method comprising:

providing an substrate surface having a contact thereon and an electrically insulated structure upon the substrate surface that is adjacent to the contact;
forming a buffer layer upon the contact and the electrically insulated structure;
forming a dielectric layer upon the buffer layer;
forming a recess in the dielectric layer adjacent to the electrically insulated structure to expose the buffer layer;
removing the buffer layer to:
extend the recess to expose the contact on the substrate surface;
and
expose a top surface on the electrically insulated structure;
reflowing the dielectric layer to contact the exposed top surface on the electrically insulated structure;
and
forming an electrically conductive structure within the recess and upon the contact on the substrate surface.

8 more elements

A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having an upper surface, the upper surface having a contact thereon and an electrically insulated gate stack upon the upper surface adjacent to the contact;
forming a buffer layer upon the contact and the electrically insulated gate stack;
forming a dielectric layer upon the buffer layer;
removing the dielectric layer selectively to the buffer layer to forming a contact hole adjacent to the electrically insulated gate stack;
removing the buffer layer selectively to the electrically insulated gate stack and the semiconductor substrate to:
extend the contact hole adjacent to the electrically insulated gate stack to expose the contact on the upper surface of the semiconductor substrate;
and
expose a top surface on the electrically insulated gate stack;
forming a liner layer within the contact hole and upon:
the dielectric layer;
the exposed top surface on the electrically insulated gate stack;
and
a lateral surface of the electrically insulated gate stack;
forming an electrically conductive structure within the contact hole and upon the contact on the upper surface of the semiconductor substrate.

11 more elements

A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having an upper surface, the upper surface having a contact thereon and a pair of electrically insulated gate stacks upon the upper surface that are separated by the contact;
forming a buffer layer upon the contact and the pair of electrically insulated gate stacks;
forming a dielectric layer upon the buffer layer;
removing the dielectric layer selectively to the buffer layer to forming a contact hole between the pair of electrically insulated gate stacks;
removing the buffer layer selectively to both the pair of electrically insulated gate stacks and the semiconductor substrate to:
extend the contact hole between the pair of electrically insulated gate stacks to expose the contact on the upper surface of the semiconductor substrate;
and
expose a top surface on each said electrically insulated gate stack;
forming a liner layer within the contact hole and upon:
the dielectric layer;
the exposed top surface on each said electrically insulated gate stack;
and
a lateral surface on each said electrically insulated gate stack;
forming an electrically conductive structure within the contact hole and upon the contact on the upper surface of the semiconductor substrate.

11 more elements

Dependencies are inferred from the claim text.

Etching process using a buffer layer

Life of this patent

Etching process using a buffer layer

Life of this patent

Abstract

Claims36