Method for forming graded LDD transistor using controlled polysilicon gate profile

A method for manufacturing MOS structures on a semiconductor substrate having first and second doping regions of different conductivity types, comprising the steps of:

• forming a gate dielectric layer over the semiconductor substrate;
• forming a polysilicon layer over said gate dielectric layer;
• forming a first mask layer over said polysilicon layer
• patterning and etching said first mask layer to form a first gate mask;
• anisotropically etching said polysilicon layer using said first gate mask to form first and second polysilicon gates, wherein said first and second polysilicon gates each include a gate part and a sidewall part with a re-entrant profile, and wherein said first polysilicon gate is over the first doping region and the second polysilicon gate is over the second doping region;
• removing said first gate mask and said second gate mask;
• depositing a third mask layer over said first and second polysilicon gates and said first and second doping regions;
• patterning and etching said third mask layer to expose said first polysilicon gate and said first doping region;
• implanting the first doping region with a first dopant at a first energy and a first concentration to form a first shallow extension junction in the first doping region around said first polysilicon gate, said implanting also performed through said sidewall part of the first polysilicon gate to form said first shallow extension junction with a first graded doping profile under said sidewall part;
• removing;
• the third mask layer;
• depositing a fourth mask layer over said first and second polysilicon gates and said first and second doping regions;
• patterning and etching said fourth mask layer to expose said second polysilicon gate and said second doping region;
• implanting said second doping region with a second dopant at a first energy and a first concentration to form a second shallow extension junction in the second doping region around said second polysilicon gate, said implanting also performed through said sidewall part of said second polysilicon gate to form said second shallow extension junction with a second graded doping profile under said sidewall part;
• removing the fourth mask layer;
• and
• removing the gate dielectric layer except under said gate parts of said first and second polysilicon gates.

A method for manufacturing an MOS structure on a semiconductor substrate, comprising the steps of:

• forming a gate oxide layer over the semiconductor substrate;
• forming a polysilicon layer over said gate oxide layer;
• forming a first mask layer over said polysilicon layer;
• forming a second mask layer over said first mask layer;
• patterning and etching said second mask layer using said first mask layer as an antireflective coating to form a second gate mask;
• patterning and etching said first mask layer to form a first gate mask;
• anisotropically etching said polysilicon layer using said first gate mask to form a polysilicon gate, wherein said polysilicon gate includes a gate part and a sidewall part with a re-entrant profile, said anistropically etching said polysilicon layer includes the steps of controlling etching parameters wherein said etching parameters include concentrations of etchants, temperature, RF power, DC bias, and magnetic field to form said re-entrant profile;
• removing said first gate mask and said second gate mask;
• implanting the semiconductor substrate with a dopant of a second conductivitiy type at a first energy and a first concentration to form a shallow extension junction around said polysilicon gate said implanting also performed through said sidewall part to form said shallow extension junction with a graded doping profile inversely proportional to the thickness of said sidewall part above said shallow extension junction;
• and
• removing the gate oxide layer except under said gate sidewall part.

A method for manufacturing a PMOS structure and an NMOS structure on a semiconductor substrate having an n-type and p-type doping regions, comprising the steps of:

• forming a gate dielectric layer over the semiconductor substrate;
• forming a polysilicon layer over said gate dielectric layer;
• forming a first mask layer over said polysilicon layer;
• patterning and etching said first mask layer to form a first gate mask;
• anisotropically etching said polysilicon layer using said first gate mask to form first and second polysilicon gates, wherein said first and second polysilicon gates each include a gate part and a sidewall part with a re-entrant profile, and wherein said first polysilicon gate is over the n-type doping region and the second polysilicon gate is over the p-type doping region;
• depositing a third mask layer over said first and second polysilicon gates and said n-type and p-type doping regions;
• patterning and etching said third mask layer to expose said first polysilicon gate and said n-type doping region;
• implanting the n-type doping region with a p-type dopant at a first energy and a first concentration to form a p-type shallow extension junction in the n-type doping region around said first polysilicon gate, said implanting also performed through said sidewall part of the first polysilicon gate to form said p-type shallow extension junction with a first graded doping profile under said sidewall part;
• depositing a fourth mask layer over said first and second polysilicon gates and said n-type and p-type doping regions;
• patterning and etching said fourth mask layer to expose said second polysilicon gate and said p-type doping region;
• implanting the p-type doping region with an n-type dopant at a first energy and a first concentration to form an n-type shallow extension junction in the p-type doping region around said second polysilicon gate, said implanting also performed through said sidewall part of said second polysilicon gate to form said n-type shallow extension junction with a second graded doping profile under said sidewall part;
• and
• removing the gate dielectric layer except under said gate parts of said first and second polysilicon gates.