Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfill

Abstract

A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance. The method comprises depositing a conformal dopant source so as to provide gap fill between gate stack conductors in the narrow space array regions and under fill between gate stack conductors in the wide space array regions; etching so that the conformal dopant source is removed from the wide space array regions and remains at least in part between the gate stack conductors in the narrow space array regions; and counter-doping gate stack conductors in the narrow space array regions by lateral diffusion of dopant from conformal dopant source through narrow space array gate stack conductor sidewalls.

Dependencies are inferred from the claim text.