Method for forming MOSFET with an elevated source/drain

A method of forming a transistor over a semiconductor substrate, said method comprising the steps of:

• forming a gate insulator layer over said semiconductor substrate;
• forming a first silicon layer over said gate insulator layer;
• forming an first dielectric layer over said first silicon layer, said first dielectric layer comprising silicon oxide;
• removing a portion of said gate insulator layer, of said first silicon layer, and of said first dielectric layer for defining a gate region;
• doping said substrate to form an extended source/drain junction in said substrate under a region uncovered by said gate region, with a low energy ion implantation process with an energy between about 0.1 to 5 KeV;
• thermally growing a second dielectric layer on said substrate and sidewalls of said first silicon layer;
• forming an undoped spacer structure on sidewalls of said gate region, said undoped spacer structure comprising silicon nitride spacers;
• forming a second silicon layer on said semiconductor substrate, said second silicon layer being deposited with a selective epitaxial process;
• removing said first dielectric layer;
• doping said first silicon layer and said second silicon layer to provide dopants for forming a source/drain junction in said substrate under a region uncovered by said gate region and said undoped spacer structure;
• forming a metal layer over said semiconductor substrate;
• performing a thermal process to said semiconductor substrate, in order to diffuse and activate dopants in said extended source/drain junction and in said second silicon layer to form said source/drain junction, and to form a metal silicide layer on said second silicon layer and said first silicon layer;
• and
• removing unreacted portion of said metal layer.