Method of forming HCMOS devices with a silicon-germanium-carbon compound semiconductor layer

A method of producing a semiconductor device including a field-effect transistor, comprising:

• a first step of forming, on a substrate, a first semiconductor layer including a Si1-x-yGexCy layer (0<x≦1, 0≦y≦1);
• a second step of forming a second semiconductor layer which comes in contact with the upper surface of said first semiconductor layer and is different in band gap from said first semiconductor layer, and in which a carrier accumulation layer serving as a channel of said field-effect transistor is formed in a portion which is adjacent to said first semiconductor layer;
• a third step of depositing a conductive layer on said second semiconductor layer and patterning said conductive layer to form a gate electrode;
• a fourth step of introducing impurities into those portions of a field-effect transistor forming region which are located at both lateral sides of said gate electrode, thus forming source-drain regions, said impurities being introduced to a depth which reaches at least said carrier accumulation layer;
• a fifth step of removing said second semiconductor layer in said source-drain regions by etching until at least said first semiconductor layer is exposed;
• and
• a sixth step of forming, on the exposed surface of said first semiconductor layer, source-drain contact layers made of conductive layers.

A method of producing a semiconductor device including a field-effect transistor comprising:

• a first step of forming, a first semiconductor layer on a substrate;
• a second step of forming a second semiconductor layer including a Si1-x-yGexCy layer (0≦x<1, 0≦y<1) which comes in contact with the upper surface of said first semiconductor layer and is different in band gap from said first semiconductor layer, and in which a carrier accumulation layer serving as a channel of said field-effect transistor is formed in a portion which is adjacent to said first semiconductor layer;
• a third step of forming a third semiconductor layer on said second semiconductor layer;
• a fourth step of forming a fourth semiconductor layer which comes in contact with the upper surface of said third semiconductor layer and is greater in band gap than said third semiconductor layer;
• a fifth step of depositing a conductive layer on said fourth semiconductor layer and patterning said conductive layer to form gate electrodes;
• a sixth step of introducing impurities into those portions of said first, second, third, and fourth semiconductor layers which are located at both lateral sides of said gate electrode, thus forming source-drain regions, said impurities being introduced to a depth which reaches at least said carrier accumulation layer;
• a seventh step of removing said fourth semiconductor layer in said source-drain regions by etching until at least said third semiconductor layer is exposed;
• and
• an eighth step of forming, on the exposed surface of said third semiconductor layer, source-drain contact layers made of conductive layers.

A method of producing a semiconductor device including an n-channel field-effect transistor and a p-channel field-effect transistor, comprising:

• a first step of forming a first Si layer on a semiconductor substrate;
• a second step of forming a first Si1-x-yGexCy layer (0<x<1, 0≦y<1) which comes in contact with the upper surface of said first Si layer and is free from strain due to lattice misfit with said first Si layer, and in which a second carrier accumulation layer serving as a channel of said p-channel field-effect transistor is formed;
• a third step of forming, on said first Si1-x-yGexCy layer, a second Si1-x-yGexCy layer (0<x<1, 0<y<1) which is different in band gap from said first Si1-x-yGexCy layer and in which a second carrier accumulation layer serving as a channel of said n-channel field-effect transistor is formed;
• a fourth step of forming a second Si layer which is in contact with the upper surface of said second Si1-x-yGexCy layer;
• a fifth step of depositing, on said second Si layer, a gate insulating layer and a conductive layer in order, and patterning said conductive layer to form gate electrodes of said n- and p-channel field effect transistors;
• and
• a sixth step of introducing, with said gate electrodes of said field-effect transistors used as masks, (i) p-type impurities into said second Si layer and said first and second Si1-x-yGexCy layers in the p-channel field-effect transistor forming region in depth which reaches at least said first carrier accumulation layer and (ii) n-type impurities into said second Si layer and said second Si1-x-yGexCy layer in the n-channel field-effect transistor forming a region at a depth which reaches at least said second carrier accumulation layer, thus forming source-drain regions of said n- and p-channel field-effect transistors.

A method of producing a semiconductor device including a field-effect transistor, comprising:

• a first step of forming a first semiconductor layer on a substrate;
• a second step of forming a second semiconductor layer which comes in contact with the upper surface of said first semiconductor layer and is greater in band gap than said first semiconductor layer;
• a third step of forming a third semiconductor layer including a Si1-x-yGexCy layer (0<x≦1, 0≦y≦1) on said second semiconductor layer;
• a fourth step of forming a fourth semiconductor layer which comes in contact with the upper surface of said third semiconductor layer and is greater in band gap than said third semiconductor layer and in which a carrier accumulation layer serving as a channel of said field-effect transistor is formed in a portion of said third semiconductor layer which is adjacent to said fourth semiconductor layer;
• a fifth step of depositing a conductive layer on said fourth semiconductor layer and patterning said conductive layer to form gate electrodes;
• a sixth step of introducing impurities into those portions of said first, second, third, and fourth semiconductor layers which are located at both lateral sides of said gate electrode, thus forming source-drain regions, said impurities being introduced to a depth which reaches at least said carrier accumulation layer;
• a seventh step of removing said fourth semiconductor layer in said source-drain regions by etching until at least said third semiconductor layer is exposed;
• and
• an eighth step of forming, on the exposed surface of said third semiconductor layer, source-drain contact layers made of conductive layers.