Method for coupling to semiconductor device in an integrated circuit having edge-defined sub-lithographic conductors
AssigneeMicron Technology, Inc.
InventorWendell P. Noble
Life of this patent
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Abstract
An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.
Claims10
A method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising the steps of:
- forming a semiconductor device in a semiconductor substrate;
- forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension;
- forming a second conductor outwardly from the semiconductor device, the second conductor adjacent to and bounded by the first conductor;
- and
- coupling a circuit component to the semiconductor device by the second conductor.
A method for forming a semiconductor memory device using a lithographic process having a minimum lithographic dimension, comprising the steps of:
- forming a transistor in a semiconductor substrate;
- forming a word line outwardly from the transistor, the word line having a width less than the minimum lithographic dimension, the word line for activating the transistor;
- forming a bit line and a conductor outwardly from the transistor that couple to the transistor, said bit line and said conductor adjacent to the word line;
- and
- forming a storage capacitor outwardly from the bit line and the conductor, said storage capacitor coupled to the transistor by the conductor.
A method for forming two memory cells having a shared bit line using a lithographic process having a minimum lithographic dimension, comprising the steps of:
- forming two transistors in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate extending outwardly from the semiconductor substrate;
- forming two word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, one word line connected to a gate of one of the two transistors and one word line connected to the other for activating the transistor;
- forming a bit line and two conductors outwardly from the transistors that couple to the transistor, the bit line coupled to the shared drain of the transistors, one conductor coupled to a source of one of the two transistors and one conductor coupled to a source of the other transistor, the bit line and the conductors adjacent to the word line;
- and
- forming two storage capacitors outwardly from the bit line and the conductors, one storage capacitor coupled to a source of one of the two transistors by one of the conductors and one storage capacitor coupled to a source of the other transistor by the other conductor.
Dependencies are inferred from the claim text.