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US 6,190,958 B1Granted
Fully self-aligned method for fabricating transistor and memory
AssigneeUnited Semiconductor Corp.
InventorShu-Ya Chuang
Life of this patent
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Abstract
A fully self-aligned method for fabricating a transistor is described. The source/drain contact opening is formed in the forming step of the gate to avoid the problem of misalignment. Therefore, the complex processes and the poly pad layer of the conventional method are not needed. A fully self-aligned method for fabricating memory is described. The memory cell and logic circuit regions have the same height during the formation process of the memory.
Claims19
A fully self-aligned method for fabricating a transistor, comprising the steps of:
- providing a semiconductor substrate;
- forming a first dielectric layer on the substrate;
- simultaneously forming a plurality of source/drain region contact openings and word line trenches on the first dielectric layer by patterning the first dielectric layer;
- forming a doped conductive layer in the source/drain contact openings and word line trenches to form a plurality of source/drain conduct plugs and first gate conductive layers, respectively;
- removing the first gate conductive layers to expose the substrate;
- performing a thermal oxidation to form a gate oxide layer on the exposed substrate and to form a plurality of source/drain regions at the interface between the source/drain contact openings and substrate;
- forming a second conductive layer in the word line trenches to form a plurality of second gate conductive layers on the gate oxide layer, wherein the second gate conductive layers have a height less than a depth of the word line trenches;
- and
- forming an insulation layer on the substrate and filling the word line trenches.
6 more elements
A fully self-aligned method for fabricating memory, comprising the steps of:
- providing a semiconductor substrate having a column and row directions;
- forming a first dielectric layer on the substrate;
- patterning the first dielectric layer for forming a plurality of source/drain contact openings and a plurality of word line trenches, wherein the word line trenches are placed parallel to the column direction;
- forming a doped conductive layer in the source/drain contact openings and the word line trenches to form a plurality of source/drain contact plugs and a plurality of first word lines, respectively;
- removing the first word lines to expose the substrate;
- performing a thermal oxidation to form a gate oxide layer on the exposed substrate and to form a source/drain region at the interface between the source/drain contact plugs and substrate;
- forming a first conductive layer on the gate oxide layer within the word line trenches to form a plurality of second word lines, wherein the second word lines are smaller in height than the word line trenches;
- forming and planarizing a first insulation layer on the substrate;
- forming a second dielectric layer on the first insulation layer;
- patterning the first insulation layer and second dielectric layer to form a plurality of bit line trenches and a capacitor contact opening, wherein the bit line trenches are placed parallel to the row direction, and the bit line trenches and capacitor contact opening expose the corresponded source/drain contact plugs;
- forming a second conductive layer in the bit line trenches and capacitor contact opening to form a plurality of bit lines and a capacitor contact plug, respectively;
- removing parts of the bit lines so that the bit lines are shorter in height than the bit line trenches;
- and
- forming a second insulation layer on the substrate and filling the bit line trenches.
11 more elements
Dependencies are inferred from the claim text.