Dense SOI programmable logic array structure

A method for fabricating a semiconductor device array on a substrate, comprising the steps of:

• forming a device layer on the substrate;
• defining silicon islands in the substrate which are laterally spaced apart from each other and are bonded to non-conductive bars extending to the substrate, wherein the device layer is atop the silicon islands;
• undercutting the silicon islands to define evacuated regions beneath the silicon islands;
• filling the evacuated regions with an insulating layer;
• forming source regions in the sides of alternate rows of the silicon islands;
• forming refractory metal source interconnects between the silicon islands and abutting the source regions of the silicon islands, wherein the source interconnects extend through the insulating layer to contact the substrate;
• forming a drain line on the sidewalls of at least some of the silicon islands, on the side of the silicon islands opposite the source regions, wherein the drain line is recessed below the level of the device layer on the silicon island;
• forming drain regions in the silicon islands;
• and
• forming gate conductor lines connecting the device layers of adjacent silicon islands in a direction orthogonal to the drain line.

A method for fabricating a semiconductor device array on a substrate, comprising the steps of:

• forming a device layer on the substrate;
• defining a first set of trenches in the substrate and extending through the device layer;
• filling the first set of trenches with silicon dioxide to form silicon dioxide bars;
• defining a second set of trenches in the substrate which extend through the device layer in a direction orthogonal to the first set of trenches to form silicon islands defined by the silicon dioxide bars and the second set of trenches;
• undercutting the silicon islands to define evacuated regions beneath the silicon islands;
• filling the evacuated regions with silicon dioxide;
• doping the sides of the silicon islands exposed by the second set of trenches to form source and drain regions therein;
• forming refractory metal contact plugs in alternate trenches of the second set of trenches abutting the source regions of the silicon islands and contacting the substrate;
• and
• forming polysilicon drain lines in alternate trenches of the second set of trenches abutting the drain regions of the silicon islands, wherein said polysilicon drain lines are recessed below the top surface of the silicon islands.

A method of fabricating a silicon-on-insulator device array on a supporting silicon substrate, comprising the steps of:

• forming a device layer on the silicon substrate by successive formation of a gate oxide layer and a polysilicon gate layer;
• defining a first set of trenches in the substrate and extending through the device layer;
• filling the first set of trenches with an insulating material to form non-conductive bars;
• defining a second set of trenches in the silicon substrate, wherein the second set of trenches extends through the device layer in a direction orthogonal to the first set of trenches to form silicon islands defined by the non-conductive bars and the sidewalls of the second set of trenches;
• etching the silicon substrate to a depth of at least one-half of the width of the silicon islands;
• undercutting the silicon islands to define evacuated regions underneath the silicon islands, wherein for each silicon island a portion of silicon remains attached to the bottom of the device layer and forms a device base, and the evacuated regions occupy the space between the device bases and the silicon substrate;
• filling the evacuated regions with an insulating layer;
• filling the second set of trenches with polysilicon to form polysilicon blocks;
• defining source trenches by etching out alternate trenches of the second set of trenches, and removing the polysilicon blocks in the alternate trenches to expose the insulating layer;
• forming a doped polysilicon liner abutting the sidewalls;
• forming source regions by thermal annealing sufficient to drive dopant from the polysilicon liner into the sides of the device bases;
• clearing out the source trenches to expose the silicon substrate;
• forming an electrical contact plug between the silicon substrate and the polysilicon liner;
• recessing the polysilicon liner so that it is below the level of the polysilicon gate layer;
• filling the source trenches with an insulating material;
• defining drain trenches by removal of the remaining polysilicon blocks, wherein said drain trenches extend through the polysilicon blocks to expose the insulating layer;
• defining contacted devices and non-contacted devices;
• forming an insulating liner on the sidewall portions abutting the device bases of the non-contacted devices;
• forming polysilicon drain lines on the sidewalls, wherein the polysilicon drain lines are doped, and are recessed below the approximate level of the top of the polysilicon gate layer;
• forming drain regions in the contacted devices by thermal annealing sufficient to drive dopant from the polysilicon drain lines into the sides of the exposed device bases of said contacted devices;
• filling the drain trenches with an insulating material;
• and
• forming gate conductor lines by connecting the polysilicon gate layers of adjacent silicon islands in a direction orthogonal to the polysilicon drain lines.