US 6,190,943 B1Granted

Chip scale packaging method

AssigneeUnited Test Center Inc.

InventorsCheng-Hui Lee, Kuo-Teh Ho, Chong-Ren Maa, Jin-Chyuan Biar

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Abstract

A chip scale packaging method is used to package a single-sided substrate and one or more semiconductor chips. The nonconductive surface of the substrate is provided with one or more chip-implanting adhesive areas by stenciling. The adhesive areas are provided with one or more through holes. The chips are implanted in the adhesive areas of the substrate such that the active surface of each chip is in contact with the adhesive area, and that the bonding pads of the active surface of the chip are corresponding in location to the through holes. Upon completion of the chip implantation, the substrate and the implanted chips are heated under pressure before the bonding pads are connected with the conductive surface of the substrate by a plurality of metal bonding wires. The chips and the through holes are subsequently provided with a passivation layer. Finally, the conductive surface of the substrate is implanted with a plurality of spherical bonding points in a grid array fashion.

Claims3

Dependent claims

A chip scale packaging method comprising the steps of:

(a) providing a substrate with a conductive surface, and a nonconductive surface which is provided with one or more chip-implanting areas whereby the chip-implanting areas are provided with one or more through holes;
(b) coating by stenciling the chip-implanting areas with a thermoplastic adhesive layer of a predetermined thickness;
(c) implanting a semiconductor chip in each of the chip-implanting areas such that an active surface of the chip is in contact with the thermoplastic adhesive layer, and that a plurality of bonding pads of the active surface are corresponding in location to the through holes;
(d) heating the substrate and the implanted chips at a predetermined temperature and under a predetermined pressure for a predetermined period of time;
(e) wire bonding the substrate and the implanted chips with a plurality of metal bonding wires whereby the metal bonding wires connect the conductive surface of the substrate with the bonding pads of the implanted chips via the through holes;
(f) providing the implanted chips and the through holes with a passivation layer of a nonconducting resin material;
and
(g) implanting the conductive surface of the substrate with a plurality of spherical bonding points in a grid array fashion.

5 more elements

Dependencies are inferred from the claim text.