US 6,190,926 B1 · Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion

Abstract

A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H2O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as UTEOS) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.

Claims31

Dependent claims

A method for yield enhancement in an integrated circuit fabrication process comprising the steps of:

providing an at least partially contamination absorbent prone first layer at least partially surrounding one element of said integrated circuit;
subjecting said integrated circuit including said first layer to a temperature sufficient to drive off at least a portion of any contaminants absorbed thereby;
further providing a relatively less contamination absorbent prone second layer in at least partial communication with said first layer;
and
passivating said integrated circuit including said first and second layers wherein any of said contaminants present in said second layer are at least partially absorbed said first layer.

2 more elements

A process for forming an integrated circuit comprising the steps of:

providing an integrated circuit structure including a semiconductor underlayer having at least one active element formed therein;
firstly depositing a bottom electrode layer of a passive element;
secondly depositing a ferroelectric dielectric layer of said passive element;
initially heating said integrated circuit structure to substantially 650° C. for substantially 5 seconds in an atmosphere of O2;
secondly heating said integrated circuit structure to substantially 850° C. for substantially 5 seconds in an atmosphere of O2;
thirdly depositing a top electrode layer of said passive element;
Depositing an interlevel dielectric layer overlying said at least one active element and said at least one passive element;
heating said integrated circuit structure to a temperature sufficient to drive off at least a portion of any moisture present in said interlevel dielectric layer;
also depositing a conductive layer electrically coupling said at least one active element and said at least one passive element;
further depositing an additional dielectric layer overlying said conductive layer;
also forming contact holes through said interlevel dielectric layer and said additional dielectric layer to provide electrical connection to at least one terminal of said at least one active element and said at least one passive element;
further forming a barrier layer overlying said additional dielectric layer;
and
passivating said integrated circuit structure.

11 more elements

Dependencies are inferred from the claim text.

Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion

Life of this patent

Yield enhancement technique for integrated circuit processing to reduce effects of undesired dielectric moisture retention and subsequent hydrogen out-diffusion

Life of this patent

Abstract

Claims31