Method of recovering a gate-level netlist from a transistor-level

A method of recovering a gate-level netlist from a transistor-level netlist, comprising the steps of:

• a) generating a functional description for each gate to be recovered using a first transistor model;
• b) generating a signature for each gate to be recovered, comprising the step of generating, for each gate to be recovered, a series of numbers where one of the numbers represents the number of inputs, outputs, and state-holding nodes of the gate to be recovered;
• where another number represents the number of valid logic value combinations in the functional description of the gate to be recovered;
• and where a number for each input, output, and state-holding node is computed by determining the number of times the particular input, output, or state-holding node is a logic value of 1 in the functional description of the gate to be recovered when those particular logic value combinations are valid and dividing that number by the total number of valid logic value combinations in the functional description of the gate to be recovered;
• c) receiving the transistor-level netlist;
• d) selecting a set of connected components from the transistor-level netlist;
• e) generating a functional description for the set of connected components using the first transistor model;
• f) generating a signature for the set of connected components, comprising the step of generating a series of numbers where one of the numbers represents the number of inputs, outputs, and state-holding nodes;
• where another number represents the number of valid logic value combinations in the functional description of the set of connected components;
• and where a number for each input, output, and state-holding node is computed by determining the number of times the particular input, output, or state-holding node is a logic value of 1 in the functional description of the set of connected components when those particular logic value combinations are valid and dividing that number by the total number of valid logic value combinations in the functional description of the set of connected components;
• g) comparing the signature of the set of connected components to the signature of each gate to be recovered;
• h) comparing the functional description of the set of connected components to the functional description of the gate to be recovered for which a match occurred in step (g);
• i) generating a functional description of the set of connected components using a second transistor model if a match occurred in step (h);
• j) comparing the functional description of the set of connected components based on the first transistor model to the functional description for the set of connected components based on the second transistor model if a functional description of the set of connected components based on the second transistor model was generated;
• k) identifying the set of connected components as the gate for which its signature matches, its functional description matches, and its functional description based on a first transistor model matches its functional description based on the second transistor model;
• and
• l) returning to step (d) if another gate at any abstraction level is desired to be recovered, otherwise stop.