Method of making a field effect transistor having a channel in an epitaxial silicon layer
AssigneeSTMicroelectronics S.r.l.
InventorRavishankar Sundaresan
Life of this patent
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Abstract
A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.
Claims14
A method for forming an integrated circuit device, comprising the steps of:
- forming a region in a substrate which is doped with impurities at a level which controls short channel device effects;
- forming a thin layer of monocrystalline silicon over the substrate adjacent the region, to a thickness of between approximately 500 and 1000 angstroms at a temperature of less than 850° C.;
- forming a gate insulating layer over the monocrystalline silicon layer;
- forming a gate electrode over the gate insulating layer;
- and
- forming source/drain regions in the monocrystalline silicon layer on either side of the gate electrode and extending into but not through the region in the substrate, leaving a channel region underneath the gate electrode in the monocrystalline silicon layer having a length of less than one half micron.
A method for forming an integrated circuit device, comprising:
- forming an isolation oxide on a substrate, the isolation oxide having an opening therethrough exposing an active region within the substrate;
- moderately doping the active region in the substrate with impurities at a level which controls short channel device effects;
- depositing a layer of undoped monocrystalline silicon on the substrate over the moderately doped active region and within the opening through the isolation oxide to a thickness of between approximately 500 and 1000 Å and at a temperature of less than 850° C.;
- forming a gate over the undoped silicon layer;
- and
- forming source/drain regions on either side of the gate, the source/drain regions extending through the undoped silicon layer and into but not through the doped active region in the substrate and defining a channel region beneath the gate having a length of less than one half micron.
Dependencies are inferred from the claim text.