Debug interface including logic generating handshake signals between a processor, an input/output port, and a trace logic
AssigneeAdvanced Micro Devices, Inc.
InventorVenkateswara Rao Madduri
Life of this patent
Estimating the term…
Abstract
A system for debugging a processor includes a debug interface including a handshake logic for communicating commands and data from a serial input/output port to a processor and to a trace control logic with a low delay. The handshake logic results in a low latency through the inclusion of a state machine that operates at the same speed as the processor. The state machine generates handshake signals to communicate among the serial input/output port, the processor, and the trace control logic.
Claims16
A processor including a debug interface for interfacing to an external debug device, the processor comprising:
- a processor core;
- a serial input/output port coupled to the processor core and communicating information between the external debug device and the processor core;
- a trace logic accessing trace information indicating instruction execution flow in the processor core;
- a debug interface coupled to the processor core, the serial input/output port, and the trace logic, the debug interface including a handshake logic generating handshake signals controlling communications between the serial input/output port and the processor core and between the trace logic and the processor core, the handshake logic including a synchronization block synchronizing the handshake signals;
- a debug register;
- and
- a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine including an access debug register state responsive to a command from the processor core to request access to the debug register.
A debug interface for interfacing a processor, including a processor core, to a debug device, the debug interface comprising:
- a serial input/output port;
- a trace logic coupled to the serial input/output port;
- and
- an interface logic coupled to the serial input/output port and coupled to the trace logic, the interface logic generating handshake signals to communicate data between the serial input/output port, the trace logic, and the processor core, the interface logic including a synchronization block for synchronizing the handshake signals and wherein operations of the serial input/output port, the trace logic, and the processor core operate mutually independently and at mutually independent clock rates.
Dependencies are inferred from the claim text.