Semiconductor device containing a self-test circuit
AssigneeNEC Corporation
InventorTadahiko Ogawa
Life of this patent
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Abstract
A semiconductor device having a self-test circuit which has an input signal generating circuit for generating a test signal in synchronization with a prescribed clock signal, a selector circuit for switching between a test mode for testing and a general normal mode and supplying the test signal generated by the input signal generating circuit to the tested circuit in the test mode, a divider circuit for obtaining the output signal from the tested circuit in response to the test signal, a latch circuit for well-timed extraction of the output signal of the tested circuit obtained by testing means, and a comparator for obtaining the output signal of the tested circuit from the latch circuit and comparing it with a prescribed expected value to evaluate.
Claims13
A semiconductor device having a testable circuit that is subject to a built-in self-test circuit comprising:
- an input signal generating means for generating a test signal in synchronization with a clock signal;
- a testing means, the testing means providing for switching between a test mode and a normal mode,
- the testing means supplying said test signal to said testable circuit when in the test mode, and obtaining an output signal from said testable circuit in response to said test signal;
- a latch means for extracting, with a specifiable timing, the output signal from said testable circuit that is obtained by said testing means;
- and
- a test result judging means for obtaining the output signal of said testable circuit from said latch means and comparing the output signal with an expected value for evaluation.
A semiconductor device having a testable circuit that is subjectable to a built-in self-test circuit comprising:
- an input signal generating means for generating a test signal in synchronization with a clock signal;
- a testing means, the testing means being capable of switching between a test mode for testing and a normal mode,
- the testing means supplying said test signal to said testable circuit when in the test mode, and obtaining an output signal from said testable circuit in response to said test signal;
- a latch means for extracting, with a specifiable timing, the output signal from said testable circuit that is obtained by said testing means;
- and
- a means for obtaining the output signal of the testable circuit from the latch means.
Dependencies are inferred from the claim text.