Semiconductor memory device having test mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsMaki Kitaoka, Tsuyoshi Hamamoto, Hideki Yamauchi, Takashi Izutsu
Life of this patent
Estimating the term…
Abstract
A counter is provided in an SRAM using a CSP (Chip Scale Package). The counter includes n+1 stages of flipflops, counts the number of pulses of an address clock signal when a test signal attains “H” level, and outputs a group of address signals. Compared with a conventional SRAM to which the group of address signals is externally input, the number of external pins necessary when a test is conducted can be reduced, and a test board can be formed using a single-layer interconnection. Consequently, reduction of costs of testing is achieved.
Claims16
A semiconductor memory device having a test mode, comprising:
- a memory array including a plurality of memory cells grouped in advance such that each memory cell group includes a prescribed number of memory cells and each memory cell group has a specific address allocated;
- a first counter including multi-stage flipflops connected in series that count number of pulses of a first clock signal input to a first stage and that output a plurality of address signals for designating the address of said memory cell group in said test mode;
- and
- a write circuit configured to write data to each of the prescribed number of memory cells belonging to the memory cell group located at the address designated by the plurality of address signals output from said first counter.
A semiconductor memory device having a test mode, comprising:
- a memory array including a plurality of memory cells grouped in advance such that memory cell groups each includes a prescribed number of memory cells and each memory cell group has a specific address allocated;
- a counter including a prescribed number of stages of flipflops connected in series that count number of pulses of an external clock signal input to a first stage and that output a prescribed number of data to be written into the prescribed number of memory cells belonging to said memory cell group in said test mode;
- and
- a write circuit configured to write the prescribed number of data output from said counter into the prescribed number of memory cells belonging to any memory cell group among a plurality of said memory cell groups.
A semiconductor memory device having a test mode, comprising:
- a memory array including a plurality of memory cells, each having a specific address allocated thereto;
- a first counter including multi-stage flipflops connected in series that count number of pulses of a first clock signal input to a first stage and that output a plurality of address signals for designating the address of said memory cell in said test mode;
- and
- a write circuit configured to write data to the memory cell located at the address designated by the plurality of address signals output from said first counter.
A semiconductor memory device having a test mode, comprising:
- a memory array including a plurality of memory cells, each having a specific address allocated thereto;
- a counter including a flipflop which counts the number of pulses of an external clock signal and which outputs data to be written into the memory cell in said test mode;
- and
- a write circuit configured to write the data output from said counter into any memory cell among said plurality of memory cells.
Dependencies are inferred from the claim text.