Transparent processor sparing
AssigneeInternational Business Machines Corporation
InventorsTimothy John Slegel, Robert E. Murray
Life of this patent
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Abstract
A computer which has multiple central processing units where at least one of the processors is a spare and unused for normal system operation, provides a mechanism for transferring the micro-architected state of a checkstopped processor to a spare processor. Each processor has a set of registers in the central processing unit where the micro-architected state of the processor is kept and these registers are accessible by millicode or microcode running on that processor. A checkstop of a processor is detected by the system, the micro-architected state of that processor is extracted and returned to the system where that state can be loaded into a spare processor in the system and processing resumed without interruption.
Claims10
A method for use in a multiprocessor computer system having
- a plurality of processor units functioning as central processor units, with a plurality of said processor units actively participating as functioning elements of said multiprocessor computer system while at least one of said processors is used as a spare processor and unused for normal system operation, with addressable system area storage accessible to all of said processors, and
- a set of registers in the processors where the micro-architected state of the processor is kept, which registers are accessible by millicode running on said processor, comprising the steps of:
- detecting the checkstop of one of the processors of the system, extracting the micro-architected state of that one processor,
- returning that one processor's micro-architected state to the system, and
- subsequently, loading that one processor's micro-architected state into said spare processor of said multiprocessor computer system, and
- transparently resuming processing in the multiprocessor computer system with said spare processor functioning as one of the active processors in normal system operation without interruption.
Dependencies are inferred from the claim text.