US 6,189,092 B1 · Pipeline processor capable of reducing branch hazards with small-scale circuit

Abstract

A processor executes a program loop at high speed using a branch target information register instruction which is set immediately before the program loop and a high-speed loop instruction which is set at an end of the program loop. When the branch target information register instruction is decoded by an instruction decoder, code in a fetched instruction buffer is sent to a branch target instruction register, and a shifted pointer in a decoded instruction counter is sent to a branch target fetch address register. After the high-speed loop instruction has been decoded by the instruction decoder and a branch condition is satisfied, the pointer in the branch target fetch address register is sent to a fetched instruction counter and to the decoded instruction counter while the code in the branch target instruction register is sent to a decoded instruction buffer. By using the shifted pointer in the decoded instruction counter, the high-speed loop instruction can be efficiently executed with small-scale hardware.

Claims17

Dependent claims

A processor for executing a program loop at a high speed using a register instruction which is set immediately before the program loop and a loop instruction which is set at an end of the program loop, the processor comprising:

a fetch unit for fetching code from a memory;
a decoding unit for decoding an instruction included in the fetched code;
and an execution unit for executing the decoded instruction,
the decoding unit including
a decoded instruction counter for storing and updating a pointer specifying an instruction that is being decoded, the pointer being a sum of a fixed shift value and an address of the instruction that is being decoded, and
the execution unit including:
storage means for storing, when the decoding unit decodes the register instruction, instruction code at a start of the program loop that has been fetched by the fetch unit into a first buffer and storing the pointer stored in the decoded instruction counter into a second buffer;
and
high-speed branch means for having the fetch unit fetch code, when the loop instruction has been decoded by the decoding unit and a branch condition is satisfied, starting from an address that corresponds to the pointer stored in the second buffer and for having the decoding unit decode the instruction code stored in the first buffer,
wherein the fixed shift value is determined so that the pointer in the second buffer corresponds to an address of code that follows the instruction code stored in the first buffer.

7 more elements

A processor for performing pipeline processing that has at least three stages including a fetch stage, a decoding stage, and an execution stage and for executing a program loop at a high speed using a register instruction which is set immediately before the program loop and a loop instruction which is set at an end of the program loop, the processor comprising:

a fetch unit for fetching code from a memory in the fetch stage;
a decoding unit for decoding an instruction included in the fetched code in the decoding stage;
and an execution unit for executing the decoded instruction in the execution stage,
the fetch unit including:
a fetched instruction counter for storing and updating a fetch address;
and
a fetched instruction buffer for storing the fetched code,
the decoding unit including:
a decoded instruction buffer for storing an instruction that is being decoded, the instruction being included in the fetched code;
and
a decoded instruction counter for storing and updating a pointer indicating the instruction that is being decoded, the pointer being a sum of a fixed shift value and an address of the instruction that is stored in the decoded instruction buffer and that is being decoded, and
the execution unit including:
a first buffer having an area for storing code;
a second buffer having an area for storing an address;
storage means for storing, when the register instruction is decoded by the decoding unit, the code stored in the fetched instruction buffer into the first buffer and storing the pointer stored in the decoded instruction counter into the second buffer,
wherein the code stored in the first buffer is instruction code at a start of the program loop,
wherein the fixed shift value is equal to a storage size of the first buffer, and
wherein the pointer stored in the second buffer corresponds to an address of code that follows the instruction code stored in the first buffer;
and
high-speed branch means, when the loop instruction has been decoded by the decoding unit and a branch condition is satisfied, for sending the pointer in the second buffer to the fetched instruction counter and sending the instruction code in the first buffer to the decoded instruction buffer.

17 more elements

a fetch unit for fetching code from a memory in the fetch stage;
a decoding unit for decoding an instruction included in the fetched code in the decoding stage;
and an execution unit for executing the decoded instruction in the execution stage,
the fetch unit including:
a fetched instruction counter for storing and updating a fetch address;
and
a fetched instruction buffer for storing the fetched code, the decoding unit including:
a decoded instruction buffer for storing an instruction that is being decoded, the instruction being included in the fetched code;
and
a decoded instruction counter for storing and updating a pointer indicating the instruction that is being decoded, the pointer being a sum of a fixed shift value and an address of the instruction that is stored in the decoded instruction buffer and that is being decoded, and
the execution unit including:
a first buffer having an area for storing code;
a second buffer having an area for storing an address;
storage means for storing, when the register instruction is decoded by the decoding unit, the code stored in the fetched instruction buffer into the first buffer and storing the pointer stored in the decoded instruction counter into the second buffer,
wherein the code stored in the first buffer is instruction code at a start of the program loop,
wherein the fixed shift value is equal to a storage size of the first buffer, and
wherein the pointer stored in the second buffer corresponds to an address of code that follows the instruction code stored in the first buffer;
and
high-speed branch means, when the loop instruction has been decoded by the decoding unit and a branch condition is satisfied, for sending the pointer in the second buffer to the fetched instruction counter and sending the instruction code in the first buffer to the decoded instruction buffer;
wherein the program loop is composed of a plurality of instructions having variable word lengths,
wherein the processor further comprises:
selection means for selecting code whose total amount is equivalent to a storage size of the decoded instruction buffer from the first buffer and from the fetched instruction buffer and outputting the selected code to the decoded instruction buffer;
and
a selection control unit for controlling the selection means to select the code first from the first buffer and then from the fetched instruction buffer,
wherein the high-speed branch means activates the selection control unit when the loop instruction has been decoded and the branch condition is satisfied, and
wherein the selection means selects the code from the fetched instruction buffer when the selection control unit is not activated.

23 more elements

a fetch unit for fetching code from a memory in the fetch stage;
a decoding unit for decoding an instruction included in the fetched code in the decoding stage;
and an execution unit for executing the decoded instruction in the execution stage, the fetch unit including:
a fetched instruction counter for storing and updating a fetch address;
and
a fetched instruction buffer for storing the fetched code, the decoding unit including:
a decoded instruction buffer for storing an instruction that is being decoded, the instruction being included in the fetched code;
and
a decoded instruction counter for storing and updating a pointer indicating the instruction that is being decoded, the pointer being a sum of a fixed shift value and an address of the instruction that is stored in the decoded instruction buffer and that is being decoded, and
the execution unit including:
a first buffer having an area for storing code;
a second buffer having an area for storing an address;
storage means for storing, when the register instruction is decoded by the decoding unit, the code stored in the fetched instruction buffer into the first buffer and storing the pointer stored in the decoded instruction counter into the second buffer,
wherein the code stored in the first buffer is instruction code at a start of the program loop,
wherein the fixed shift value is equal to a storage size of the first buffer, and
wherein the pointer stored in the second buffer corresponds to an address of code that follows the instruction code stored in the first buffer;
and
high-speed branch means, when the loop instruction has been decoded by the decoding unit and a branch condition is satisfied, for sending the pointer in the second buffer to the fetched instruction counter and sending the instruction code in the first buffer to the decoded instruction buffer;
wherein the fetched instruction counter includes:
an address register for storing the fetch address;
and
a first adder for incrementing the fetch address in the address register by a predetermined value,
wherein the decoded instruction counter includes:
a pointer register for storing the pointer;
and
a second adder for incrementing the pointer in the pointer register by a word length of a decoded instruction,
wherein, when the branch instruction with the relative address is decoded by the decoding unit, the branch means:
has the second adder subtract the fixed shift value from the pointer in the pointer register;
stores a sum of a subtracting result and the relative address into the address register as a branch target address;
has the first adder add the predetermined value to the branch target address stored in the address register, the predetermined value being the fixed shift value;
and
stores an adding result into the pointer register.

29 more elements

Dependencies are inferred from the claim text.

Pipeline processor capable of reducing branch hazards with small-scale circuit

Life of this patent

Pipeline processor capable of reducing branch hazards with small-scale circuit

Life of this patent

Abstract

Claims17