Digital signal processor with variable width instructions

A method of operating a digital signal processor having a digital data bus, a register file connected to said digital data bus and storing digital data, an address generator connected to said register file and responding to command signals to address digital data in said register file, and a logic unit connected to said register file and responding to command signals to perform digital data processing upon data in said register file, the method comprising:

• storing in a program memory instructions comprising a program for said digital signal processor, said instructions including short instructions having a first number of digital signals and long instructions having a second number of digital signals greater than said first number of digital signals of said short instructions, wherein said program memory comprises a first section and a second section, said long instructions being stored in said first section and said second section, each said short instruction being stored in a single entry of said first or second sections;
• retrieving said instructions,
• responding to said instructions by generating command signals to said address generator to retrieve and store data to and from said register file via said digital data bus, or by generating command signals to said logic unit to perform digital data processing upon data in said register file,
• said responding step including responding to short and long instructions from either said first or said second sections of a program memory in a first mode, and responding only to long instructions from both said first section and said second sections of said program memory in a second mode.

A method of assembling a source program of code lines into an object program of instructions for use in operating a digital signal processor, the method comprising:

• grouping said code lines of said source program into at least a first group and a second group,
• assembling a first module of short instructions of said program by scanning each code line in said first group and generating from said code lines in said first group short or long instructions of said first module, said short instructions having a first number of digital signals and said long instructions having a second number of digital signals greater than said first number of digital signals of said short instructions, said short and long instructions being mixed in said first assembled module,
• assembling a second module of long instructions of said program by scanning each code line in said second group and generating therefrom long instructions of said second module,
• linking said first and second modules of instructions together into said object program, said linking comprising determining whether said second module instructions will be aligned with a program memory storing said object program, and if not, inserting instructions between said first and second modules to align instructions of said second module with said program memory.

A digital signal processor, comprising

• a program memory having a plurality of rows storing instructions comprising a program for said digital signal processor, said instructions including short instructions having a first number of digital signals and long instructions having a second number of digital signals greater than said first number of digital signals of said short instructions;
• a program control unit retrieving instructions from said program memory, and responding to said instructions by generating command signals controlling operations of other units of said digital signal processor, said program control unit having a first mode in which said program control unit retrieves and responds to short instructions, and a second mode in which said program control unit retrieves and responds to long instructions, said program control unit retrieving said long instructions in said second mode from positions in predetermined alignment with rows of said program memory, said program control unit retrieving one or more instructions in said first mode from positions that are misaligned with rows of said digital memory,
• a register file storing digital data;
• an address generator unit connected to said digital data bus, said register file and to said program control unit and responding to command signals to retrieve and store data from and to said digital data memory to and from said register file via said digital data bus;
• and
• at least one logic unit connected to said program control unit and to said register file and responding to command signals to perform digital data processing upon data in said register file.