Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location

A method for scheduling instructions for execution in a computer processing system implementing out-of-order execution, the method comprising the steps of:

• selecting and moving a next instruction from its current position in a sequence of instructions to an earlier position;
• determining whether the selected instruction may reference a memory location for read-access;
• determining whether the selected instruction is an in-order instruction with respect to non-selected instructions which may reference the memory location for read-access, when the selected instruction may reference the memory location for read-access;
• establishing a bypass sequence to be performed during an execution of the selected instruction and which passes datums previously read-accessed by the non-selected instructions to the selected instruction, when the selected instruction is an in-order instruction with respect to the non-selected instructions and addresses of memory locations from which the non-selected instructions have read-accessed the datums are the same as an address of the memory location from which the selected instruction is to read-access a datum;
• determining whether the selected instruction is an out-of-order instruction with respect to the non-selected instructions, when the selected instruction may reference the memory location for read-access;
• adding a mechanism for storing a record of the selected instruction for future reference by the non-selected instructions, when the selected instruction is an out-of-order instruction with respect to the non-selected instructions.

A method for enforcing consistency between data values obtained during multiple read-accesses from a memory location in a computer processing system wherein sequences of instructions are executed by at least one processor unit, the multiple read-accesses initiated by an out-of-order load instruction and at least one other load instruction, the method comprising the steps of:

• executing the out-of-order load instruction to control the at least one processor unit to at least read-access a first datum from the memory location identified by the out-of order load instruction;
• creating a record of the out-of-order load instruction for use by the at least one other load instruction, wherein the record includes an address of the memory location from which the first datum was loaded and a value associated with the first datum;
• and
• executing the at least one other load instruction and controlling the at least one processor unit during said executing of the at least one other load instruction to perform the following steps:
• determining whether the address of the memory location from which the out-of-order instruction loaded the first datum is one of overlapping and the same as an address from which the at least one other load instruction is to load a datum;
• and
• passing one of the first datum and a portion thereof from the record to the at least one other load instruction, when the addresses are one of the same and overlapping, respectively.

An apparatus for enforcing consistency between data values obtained during multiple read-accesses from a location in a memory subsystem of a computer processing system, wherein sequences of instructions are executed by at least one processor unit, the multiple read-accesses initiated by at least one out-of-order load instruction and an in-order load instruction, the apparatus comprising:

• storing means for storing a record of the at least one out-of-order load instruction, wherein the record comprises an address of the location in the memory subsystem from which a datum was read-accessed, and a value associated with the datum;
• comparison logic for comparing the address of the location in the memory subsystem from which the at least one out-of-order load instruction read-accessed the datum with an address of the location in the memory subsystem from which the in-order load instruction is to read-access a datum, when processing the in-order instruction;
• control logic for directing said storing means to store the record, for accessing the record of the at least one out-of-order instruction to supply the address to said comparison logic;
• and
• a data selection mechanism, under the control of said control logic, for supplying one of the value stored in said storing means and a part thereof to the in-order instruction, when the addresses compared by said comparison logic are one of equal and overlapping, respectively.

An apparatus for enforcing consistency between data obtained during multiple read-accesses from a location in a memory subsystem of a computer processing system, wherein sequences of instructions are executed by at least one processor unit, the multiple read-accesses initiated by at least one previously executed load instruction and a currently executing load instruction, the apparatus comprising:

• storing means for storing a record of the at least one previously executed instruction, wherein the record comprises an address of the location in the memory subsystem from which data was read-accessed and the data;
• an interference test and priority encoder for comparing the address of the location from which the at least one previously executed instruction read-accessed the data with an address of the location from which the currently executing instruction is to read-access data, and determining whether the at least one previously executed instruction has associated therewith a later instruction number than the currently executing instruction, when processing the currently executing instruction;
• control logic for directing said storing means to store the record, for accessing the record of the at least one previously executed instruction to supply the address to said interference test and priority encoder;
• and
• a data selection mechanism, under the control of said interference test and priority encoding logic, for supplying one of the data stored in said storing means and a part thereof to the currently executing instruction, when the addresses compared by said interference test and priority encoder are one of equal and overlapping, respectively, and the at least one previously executed instruction has the later instruction number associated therewith.