Superscalar instruction decoder including an instruction queue

An apparatus comprising:

• an instruction queue including storage for a plurality of CISC instructions, wherein the CISC instructions map to one or more RISC-like operations (“ROPs”) in accordance with a predefined CISC instruction to ROP mapping;
• a multiplexer coupled to the instruction queue and responsive to predecode information indicative of a mapping number of ROPs to which an associated one of the CISC instruction maps, the multiplexer having a plurality “m” of outputs to direct information from ones of the CISC instructions to mapping numbers of the multiplexer outputs, up to “m” CISC instructions;
• and
• a plurality “m” of CISC instruction to ROP conversion paths, each conversion path coupled to a respective multiplexer output to convert a CISC instruction directed thereto to a respective one of the ROPs to which the CISC instruction maps.

A method of decoding plural complex instruction set computer (“CISC”) instructions into plural RISC-ike operations (“ROPs”) for parallel dispatch to a superscalar processor core, the method comprising:

• storing a plurality, “n” or greater, of the CISC instructions in an instruction queue;
• selectively routing “n” of the CISC instructions to a plurality “p” (p>n) of dispatch positions in accordance with predefined mappings of each of the “n” CISC instructions to one or more corresponding ROPs;
• converting, simultaneously for each of the dispatch positions, each of the “n” instructions into the corresponding one or more ROPs, wherein at least one of the “n” CISC instructions is converted to at least two corresponding ROPs, and wherein the simultaneously converted ROPs total “p” (p>n);
• driving the “p” converted ROPs from the “p” dispatch positions in parallel to the superscalar processor core.

A method comprising,

• directing information from each of plural complex instruction set computer (“CISC”) instructions to conversion paths;
• simultaneously converting the plural CISC instructions along the conversion paths and supplying plural RISC-like operations (“ROPs”) in
• accordance with a predefined mapping of each of the CISC instructions to corresponding of the ROPs,
• wherein at least one of the plural CISC instructions so converted maps to a set of plural of the supplied ROPs.

An apparatus for decoding CISC instructions into RISC-like operations (“ROPs”) for dispatch to a RISC processor, wherein the CISC instructions map to respective numbers of ROPs in accordance with a predefined CISC instruction to ROP mapping, the apparatus comprising:

• means for aligning CISC opcodes and addressing information of the CISC instructions into dispatch positions based on the numbers of ROPs to which the CISC instructions map;
• means for decoding the CISC opcodes and addressing information into ROP opcodes and addressing information based on, for each CISC instruction, the position of the dispatch position decoding the CISC instruction relative to other dispatch positions decoding the same CISC instruction;
• and
• means for driving the ROP opcodes and addressing information from the dispatch positions in parallel to the RISC processor.

An instruction path for a complex instruction set computer (“CISC”) processor having a reduced instruction set computer (“RISC”) superscalar core, instruction path comprising:

• a plurality of dispatch positions;
• distribution logic coupled to an instruction store to direct a first CISC instruction, which maps to a sequence of one or more RISC-like operations (“ROPs”) in accordance with a predefined CISC instruction to ROP mapping, to a selectively-determined subset of the dispatch positions, in parallel;
• means associated with each of the subset of dispatch positions for converting a CISC instruction directed thereto into a respective one of the ROPs of the ROP sequence, in parallel;
• and
• means for dispatching converted ROPs to the superscalar RISC core, in parallel.

A processor comprising:

• a queue having a head-of-queue position and containing and instruction at the head-of-queue position, the head-of-queue instruction being a first-type instruction having a first type opcode and first-to-second type opcode mapping indicia;
• an instruction decoder comprising:
• a multiplexer coupled to the queue;
• and
• a plurality of first-to-second type opcode converters having an hierarchical relationship with one another, a first subset of the first-to-second type opcode converters of a size determined by the mapping indicia of the head-of-queue instruction being coupled by the multiplexer to the first type opcode of the head-of-queue instruction;
• and
• a superscalar processor core having a plurality of hierarchical second-type instruction inputs respectively coupled to outputs of the first-to-second type opcode converters in accordance with the hierarchy thereof.

An instruction decoder comprising:

• a plurality of hierarchically-araanged first type instruction inputs, each comprising a first type opcode input field, an opcode marker input field, and a first-to-second type opcode mapping indicia input field;
• a switch array having inputs coupled to the opcode input fields;
• a plurality of first-to-second type opcode converters having inputs coupled to outputs of the switch array;
• and
• control logic having inputs coupled to the opcode marker input fields and the mapping indicia input fields, the control logic having an output coupled to the switch array and being responsive to values in the opcode marker input fields and the mapping indicia input fields to couple a lowest ordered opcode input field of the switch array having an asserted value in the opcode marker field to a first subset of the first-to-second type opcode converters through the switch array, the first subset of the first-to-second type opcode converters having a size determined by the mapping indicia input field of the lowest order instruction input.