Circuit for the management of memories in a multiple-user environment with access request and priority

An information processing system comprising:

• at least two user devices each comprising one local memory, the local memory being used as a working memory for each of the user devices;
• at least one priority access processor generating a priority interrupt request for interrupting requests from the user devices;
• a central memory whose contents can be used by one of the at least two user devices and the at least one priority access processor;
• a circuit for managing the central memory that receives requests from the user devices and, as a function of the priority interrupt request and of internal information, gives signals to drive the central memory and data exchanges between the central memory and the user devices;
• a first-in/first-out (FIFO) buffer memory connected firstly between the management circuit and the central memory and secondly between the user devices and the central memory, the FIFO buffer memory comprising
• at least one input buffer whose data outputs are connected to the central memory, and
• at least one output buffer whose data inputs are connected to the central memory;
• and
• the circuit for managing the central memory enabling the priority access processor to replace the FIFO buffer memory to directly drive the central memory.

A method for managing a central memory shared between at least two user devices, each having available one local memory by means of a request management circuit to manage data exchanges between the local memories and the central memory and at least one priority access processor generating a priority interrupt request for interrupting requests from the user devices, the method comprising the steps of:

• using the request management circuit for interpreting requests sent by the user devices for data exchange and for producing control signals to drive the central memory during an exchange of data between the central memory and one of the user devices;
• storing the control signals in a first-in/first-out (FIFO) buffer memory that regulates a bit rate of the control signals between the request management circuit and the central memory;
• and
• using the priority access processor to replace the buffer memory to drive the central memory.