Method of emulating a dual-port memory device using an internally cached static random access memory architecture
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
Life of this patent
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Abstract
A circuit for internally caching a memory device having a main memory is comprised of a cache memory of smaller size than the main memory for storing certain of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.
Claims22
A method of emulating a dual-port memory device with a memory device having a single port main memory array and first and second cache memory arrays, said method comprising the following steps which are preformed internally of the memory device:
- storing data entries in the main memory array;
- storing multiple data entries which are the same as data entries stored in the main memory array in the first and second cache memory arrays, the first and second cache memory arrays being of different sizes;
- mapping the multiple data entries stored in the first and second cache memory arrays to the main memory array;
- generating a first ready signal in response to data entries stored in the first cache memory array;
- generating a second ready signal in response to data entries stored in the second cache memory array;
- and
- controlling the movement of data entries into and out of the memory device in response to the first and second signals to enable a device having a single port main memory array to emulate a dual-port memory device having ports of different bandwidths.
A method of enabling a device having a single port main memory array to emulate a device having a multi-port memory array comprising the following steps which are performed internally of the memory device:
- storing data entries in the main memory array;
- storing multiple data entries which are the same as data entries stored in the main memory array in a plurality of cache memory arrays, each of the cache memory arrays being of a different size;
- mapping the information stored in the plurality of cache memory arrays to the main memory array;
- generating a plurality of ready signals in response to information stored in the plurality of cache memory arrays;
- and
- controlling the movement of data entries out of the device in response to the plurality of signals to enable a device having a single port main memory array to emulate a multi-port memory device having ports of different bandwidths.
A method of emulating a multi-port memory device using a single port main memory array comprising the following steps which are preformed internally of the device:
- storing, in a plurality of cache memory arrays of different size, multiple data entries which are the same as data entries retrieved from a main memory array;
- identifying which data entries are stored in the plurality of cache memory arrays;
- and
- simultaneously retrieving data entries from more than one of the cache memory arrays to enable a device having a single port main memory array to emulated a multi-port device wherein the ports have different bandwidths.
A method of operating a multi-port memory device having a single port main memory array to enable the device to emulate a device having a multi-port main memory array, said method being preformed internally of the device and comprising:
- storing, in a plurality of cache memory arrays of different sizes, multiple data entries which are the same as data entries retrieved from the main memory array;
- storing tag information in a plurality of tag memory arrays, the tag information corresponding to the data entries stored in the plurality of cache memory arrays;
- simultaneously receiving address information corresponding to more than one data entry;
- and
- outputting from the device data entries corresponding to the received address information in a manner such that an average access time of the memory device is different for each port and less than an average access time of the single port memory array.
A method of operating a multi-port memory device having a single port main memory array, said method performed internally of said device and comprising:
- providing a plurality of cache memory arrays, at least two being of a different size, and the total number of cache memory arrays being equal to the number of ports of the multi-port memory device, and providing a plurality of tag memory arrays, one responsive to each of the cache memory arrays;
- simultaneously receiving address information at more than one port of the device, said address information corresponding to data entries;
- and
- simultaneously outputting data entries from the device corresponding to the received address information to enable a device having a single port main memory array to emulate a multi-port memory device having at least two ports of different bandwidth.
A method of operating a multi-port memory device having a single port main memory array, said method performed internally of said device and comprising:
- providing a plurality of variously sized cache memory arrays equal in number to the number of ports, and providing a plurality of tag memory arrays, one tag memory array being associated with each of the cache memory arrays;
- receiving address information at more than one port of the device, said address information corresponding to data entries;
- and
- outputting data entries from the device corresponding to the received address information on the port at which the address information was received in a manner such that an average access time of the memory device is different for at least two ports and less than an average access time of the single port memory array.
Dependencies are inferred from the claim text.