Performance monitoring of cache misses and instructions completed for instruction parallelism analysis
AssigneeInternational Business Machines Corporation
InventorsFrank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
Life of this patent
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Abstract
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
Claims16
In a performance monitor in a data processing system, a method comprising the steps of:
- counting high signals from an ICACHE and a DCACHE as a result of a cache miss;
- and
- counting threshold completed signals (“TCS”) associated with completed instructions;
- wherein the step of counting the threshold completed signals further comprises:
- receiving a high signal from a cache and the TCS signal;
- counting a number of cycles when any cache miss is in progress and a threshold number of instructions are completed in response to the steps of receiving the high signal from the cache and the TCS signal;
- and
- counting a number of times when any cache miss occurs and a threshold number of instructions are completed in response to the step of receiving the high signal from the cache and the TCS signal.
A performance monitor in a data processing system, comprising:
- circuitry for counting high signals from an ICACHE and a DCACHE as a result of a cache miss;
- and
- circuitry for counting threshold completed signals (“TCS”) associated with completed instructions;
- where the circuit for counting threshold completed signals further comprises:
- circuitry for receiving a high signal from a cache and the TCS signal;
- circuitry for counting a number of cycles when any cache miss is in progress an a threshold number of instructions are completed in response to the circuitry for receiving the high signal from the cache and the TCS signal;
- and
- circuitry for counting a number of times when any cache miss occurs and a threshold number of instructions are completed in response to the circuitry for receiving the high signal from the cache and the TCS signal.
Dependencies are inferred from the claim text.