Clock extraction circuit
AssigneeFujitsu Limited
InventorsHisaya Sakamoto, Akihiko Sugata, Akimitsu Miyazaki, Tetsuya Kiyonaga
Life of this patent
Estimating the term…
Abstract
Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.
Claims7
A clock extraction circuit for extracting a clock signal, which furnishes timing for discriminating a data signal, from the data signal, comprising:
- a timing extraction unit to extract the clock signal from the data signal;
- and
- a filter having an upper limited frequency sufficiently lower than the bit rate of the data;
- wherein the data signal is input to said timing extraction unit via said filter.
A clock extraction circuit for extracting a clock signal, which furnishes timing for discriminating a data signal, from the data signal, comprising:
- a timing extraction unit to extract the clock signal from the data signal;
- and
- a slicer amplifier to vary slice level to improve the duty cycle of the data signal;
- wherein the data signal is input to said timing extraction unit via said slicer amplifier.
Dependencies are inferred from the claim text.