Parallel M-sequence generator circuit
AssigneeTexas Instruments Incorporated
InventorHirohisa Yamaguchi
Life of this patent
Estimating the term…
Abstract
A parallel M-sequence generator is disclosed which outputs an identical bit stream of a serial M-sequence generator of equal chip length. In a parallel N-bit implementation, the first N bits of the sequence are read at the output, the remaining bits are shifted, and the new N bits are generated, all in one clock cycle. The effect of obtaining N bits at the output is to multiply the present contents of the shift register by a companion matrix of the Nth order. Linear combining elements (e.g. XOR gates) are selectively positioned to combine the contents of various delay elements of the parallel structure and feedback the results to other delay elements in order to produce the identical output of the serial structure.
Claims21
A method for generating a maximal length sequence of data, comprising the steps of:
- providing a plurality of blocks of shift registers, each of the blocks having a length N;
- connecting the blocks in a parallel configuration in an order from an input block to an output block, wherein each of the outputs of the shift registers in a proceeding one of the blocks is input to the input of corresponding ones of the shift registers in the adjacent one of the blocks with the last of the blocks providing an N-bit output word, wherein the plurality of blocks further comprises a remainder block having a length less than N and comprising the first of the blocks in the parallel configuration;
- and
- interconnecting the outputs of select ones of the shift registers in the blocks through a feedback operator to inputs of select ones of the shift registers in the blocks in accordance with a maximal length sequence algorithm, wherein an initial sequence of data stored in the blocks of shift registers is shifted through the blocks of shift registers in N-bit increments to realize a maximal length sequence defined by the algorithm.
A maximal length sequence generator, comprising:
- a plurality of blocks of shift registers, each of said blocks having a length N;
- a connection network for connecting said blocks in a parallel configuration in an order from an input block to an output block, wherein each of the outputs of said shift registers in a proceeding one of said blocks is input to the input of corresponding ones of said shift registers in the adjacent one of said blocks, with the last of said blocks providing an N-bit output word, wherein said plurality of blocks further comprises a remainder block having a length less than N and comprising the first of said blocks in said parallel configuration;
- and
- a feedback logic network for interconnecting the outputs of select ones of said shift registers in said blocks through a feedback operator to inputs of select ones of said shift registers in said blocks in accordance with a maximal length sequence algorithm, wherein an initial sequence of data stored in said blocks of shift registers is shifted through said blocks of shift registers in N-bit increments to realize a maximal length sequence defined by said algorithm.
A communication system, comprising:
- a transmitting section for sending a signal, comprising
- a mixing circuit for mixing the signal with carrier frequencies,
- a signal transmission device, and
- a maximal sequence generator;
- and
- a receiving section for receiving the signal, comprising
- a mixing circuit for mixing the signal with carrier frequencies,
- a signal reception device, and
- a maximal sequence generator, wherein the maximal sequence generator of the transmitting section and the receiving section comprising
- a plurality of blocks of shift registers, each of said blocks having a length N;
- a connection network for connecting said blocks in a parallel configuration in an order from an input block to an output block, wherein each of the outputs of said shift registers in a proceeding one of said blocks is input to the input of corresponding ones of said shift registers in the adjacent one of said blocks, with the last of said blocks providing an N-bit output word, wherein said plurality of blocks further comprises a remainder block having a length less than N and comprising the first of said blocks in said parallel configuration;
- and
- a feedback logic network for interconnecting the outputs of select ones of said shift registers in said blocks through a feedback operator to inputs of select ones of said shift registers in said blocks in accordance with a maximal length sequence algorithm, wherein an initial sequence of data stored in said blocks of shift registers is shifted through said blocks of shift registers in N-bit increments to realize maximal length sequence defined by said algorithm.
Dependencies are inferred from the claim text.