Synchronous digital transmission system

A network element of a transmission system for digital signals that are combined into a multiplex signal, in which the digital signals are inserted in the form of bytes into frames of an established frame format, where each frame has areas for control data and areas for payload data, with an adapter circuit for balancing phase variations in a multiplex signal which can be supplied to the network element, said adapter circuit having

• a buffer memory (1) for payload data bytes,
• a write address generator (2) which controls writing into the buffer memory (1) in accordance with a write cycle which comprises a first number of payload data bytes as they occur in the multiplex signal and a pause of a first length when the overhead data bytes occur in the multiplex signal,
• a read address generator (3) which controls reading from the buffer memory (1) in according with a read cycle which comprises a second number of payload data bytes to be read and a pause of a second length for the overhead data bytes to be inserted, and
• a sort facility (5) which sorts the read payload data bytes read from the buffer memory (1) in accordance with the read cycle so that a multiplex signal transmitted by the network element has the established frame format, characterized in that
• the second number is less than the first number and the second length is shorter than the first length.

A network element of a transmission system for digital signals that are combined into a multiplex signal, in which the digital signals are inserted in the form of bytes into frames of an established frame format, where each frame has areas for control data and areas for payload data, with an adapter circuit for balancing phase variations in a multiplex signal which can be supplied to the network element, said adapter circuit having:

• a buffer memory (1) for payload data bytes:
• a write address generator (2) which controls writing into the buffer memory (1) in accordance with a write cycle which comprises a first number of payload data bytes as they occur in the multiplex signal and a pause of a first length when the overhead data bytes occur in the multiplex signal;
• a read address generator (3) which controls reading from the buffer memory (1) in accordance with a read cycle which comprises a second number of payload data bytes to be read and a pause of a second length for the overhead data bytes to be inserted;
• and
• a sort facility (5) which sorts the read payload data bytes read from the buffer memory (1) in accordance with the read cycle so that a multiplex signal transmitted by the network element has the established frame format, characterized in that the second number is less than the first number and the second length is shorter than the first length and the sort facility (5) is connected to a pointer-generator (4) located in the adapter circuit, which is connected to the read address generator (3) and the buffer memory (1), and supplies the payload data bytes and the control data bytes to be sorted to the sort facility (5).

A transmission system for digital signals that are combined into a multiplex signal, in which the digital signals are inserted in the form of bytes into frames of an established frame format, where each frame has areas for overhead data and areas for payload data, in which several network elements that are interconnected by transmission media are located, each comprising an adapter circuit to balance phase variations in an incoming multiplex signal, and where the adapter circuit has:

• a buffer memory (1) for payload data bytes;
• a write address generator (2) which controls writing into the buffer memory (1) in accordance with a write cycle which comprises a first number of payload data bytes as they occur in the multiplex signal and a pause of a first length when the overhead data bytes occur in the multiplex signal;
• a read address generator (3) which controls reading from the buffer memory (1) in accordance with a read cycle which comprises a second number of payload data bytes to be read and a pause of a second length for the overhead data bytes to be inserted:
• and
• a sort facility (5) which sorts the payload data bytes read from the buffer memory (1) in accordance with the read cycle so that a multiplex signal transmitted by the network element has the established frame format, characterized in that the second number is less than the first number and the second length is shorter than the first length, and the sort facility (5) is connected to a pointer-generator (4) located in the adapter circuit, which is connected to the read address generator (3) and the buffer memory (1), and supplies the payload data bytes and the control data bytes to be sorted to the sort facility (5).