Circuit arrangement for sensing errors in bit patterns
AssigneeDeutsche Telekom AG
InventorWerner Herzog
Life of this patent
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Abstract
A circuit arrangement for sensing errors in bit patterns for recording and plotting the occurrence in time, precisely to a bit, of transmission errors in a binary test signal. A pulse-generating device (5), which is fed a bit error signal sequence (BFS) generates a pulse (IS) in response to every signal change. A counting device (11), increments a counter as a function of a supplied bit timing (BT) and resets it to count value 1 when the pulse (IS) from the pulse-generating device (5) is applied. A buffer device (13) linked to the outputs of the counting device stores the counter contents of the counting device (11) in response to the application of a pulse (IS). An evaluation device (17,19,23) is fed, stores and displays the buffered counter contents.
Claims15
A circuit arrangement for sensing with single-bit precision a bit error signal sequence produced by a comparator circuit on the basis of a test signal and a substantially identical reference signal, the circuit arrangement comprising:
- a pulse-generating device for receiving the bit error signal sequence, the pulse-generating device generating a pulse in response to every signal change;
- a counting device for receiving the pulse from the pulse-generating device, the counting device including a counter, the counting device incrementing the counter as a function of a supplied bit timing and resetting the counter to the count value 1 when the pulse from the pulse-generating device is applied;
- a buffer device for receiving output from the counting device, the buffer device storing the counter content of the counting device in response to the application of the pulse;
- and
- an evaluation device for receiving the buffered counter contents.
Dependencies are inferred from the claim text.