Synchronous semiconductor memory device having input circuit with reduced power consumption

A synchronous semiconductor memory device comprising:

• a command input circuit, for latching an external command in synchronization with an internal clock;
• and
• a command decoder, for decoding said latched external command;
• a chip select signal input circuit, receiving an external chip select signal, for activating an enable signal in response to activation of said external chip select signal, for deactivating said enable signal in response to deactivation of said external chip select signal, for generating an internal chip select signal by synchronizing said external chip select signal with said internal clock;
• a clock input circuit, for outputting said internal clock depending on an external clock while said enable signal is active;
• and
• a decode enabling circuit, for generating a command decoder activating signal by synchronizing said internal chip select signal with said internal clock.