Synchronous semiconductor memory

A synchronous semiconductor memory device, comprising:

• an input/output (I/O) control system that can receive an internal control signal and a row address enable (RASE) signal, the I/O control system activating at least one circuit control signal in response to the internal control signal when the RASE signal has a first value, and disabling the circuit control signal in response to the RASE signal having a second value;
• and
• at least one I/O circuit coupled to external I/O values that can drive internal I/O signals in response to the external I/O values when enabled, the at least one I/O circuit being enabled when the at least one circuit control signal is activated, and disabled when the at least one circuit control signal is disabled.

A synchronous dynamic random access memory (SDRAM) having a precharge stand-by state, power-down mode, a non-power down mode, and column address latency that may be set to a value of at least one clock cycle, the SDRAM comprising:

• a plurality of external input/output (I/O) signal nodes;
• a data I/O system coupled to the external I/O signal nodes that drives internal nodes in response to the potential of the external I/O signal nodes, the data I/O circuit being disabled when the SDRAM is in the non-power down mode and the precharge stand-by state.

The SDRAM of 18, further including:

• a first-stage control circuit that generates a first stage control signal that is enabled in a non-power down mode and disabled in a power down mode;
• and
• the data I/O system receives the first stage control signal and a row address enable signal as inputs, and provides a data I/O system signal as an output, the data I/O system signal being the logical combination of the first stage control signal and the row address enable signal, the row address enable signal being inactive in a precharge standby state.