Integrated semiconductor memory with control device for clock-synchronous writing and reading

An integrated semiconductor memory, comprising:

• a multiplicity of storage cells;
• a control device for clock-synchronous writing and for reading a data value to and from one of said multiplicity of storage cells, said control device controlling the writing such that the data value represented in a data signal received by the control device is coupled to a second clock signal and the second clock signal is coupled to a first clock signal received by said control device, said control device controlling the reading such that, in a first operating mode, the data value represented by the data signal being coupled only to the first clock signal, and in a second operating mode the data value represented by the data signal being coupled to the second clock signal and the second clock signal is coupled to the first clock signal;
• and
• a device for producing a control signal to be fed to said control device for switching over between the first operating mode and the second operating mode.