Semiconductor memory device allowing reduction in power consumption during standby

A synchronous signal generating circuit, comprising:

• a phase comparator comparing a phase of an internal clock signal with a phase of an external clock signal;
• and
• an internal clock generator generating the internal clock signal having a frequency associated with a comparison result of said phase comparator in a first mode and a frequency designated in a second mode;
• wherein
• the internal clock signal is capable of having a larger frequency than the external clock signal in the second mode.

A synchronous signal generating circuit, comprising:

• a phase comparator comparing a phase of an internal clock signal with a phase of an external clock signal;
• and
• an internal clock generator generating the internal clock signal having a frequency associated with a comparison result of said phase comparator in a first mode and a frequency designated in a second mode;
• wherein said phase comparator is deactivated in the second mode.

A synchronous signal generating circuit, comprising:

• a phase comparator comparing a phase of an internal clock signal with a phase of an external clock signal;
• an internal clock generator generating the internal clock signal having a frequency associated with a comparison result of said phase comparator in a first mode and a frequency designated in a second mode and;
• a register, wherein
• the frequency of the internal clock signal is designated by a value stored in said register in the second mode.

A synchronous signal generating circuit, comprising:

• a phase comparator comparing a phase of an internal clock signal with a phase of an external clock signal;
• and
• an internal clock generator generating the internal clock signal having a frequency associated with a comparison result of said phase comparator in a first mode and a frequency designated in a second mode,
• wherein said synchronous signal generating circuit is set to a free-run state, in which the frequency of the internal clock signal is independent of the external clock signal, in the second mode.