US 6,188,634 B1Granted

Semiconductor memory having memory bank decoders disposed symmetrically on a chip

AssigneeInfineon Technologies AG

InventorThoai-Thai Le

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Abstract

In semiconductor memories, memory banks are activated via memory bank decoders. The memory bank decoders assigned to different groups of memory banks have a layout that is symmetrical with respect to an axis of mirror symmetry. A changeover is made between the memory bank decoders by a predecoder. For this purpose, the predecoder generates enable and address signals for the memory banks. This enables the memory bank decoders to be disposed on the semiconductor chip in direct proximity to the respectively assigned memory banks.

Claims8

Dependent claims

A semiconductor memory, comprising:

a number of memory banks, each including:
a memory cell array having a multiplicity of memory cells disposed in a matrix-like manner having rows and columns and defining a matrix of memory cells;
and
an address decoder for selecting one of a row and a column of said matrix of memory cells;
means for feeding in an address containing a number of address bits for selecting one of said row and said column of one of said memory cells by addressing said address decoder;
memory bank decoders, including:
a first memory bank decoder connected to a first group of said memory banks, said first memory bank decoder having an input side, an output side and generating a first respective bank selection signal available at said output side for each memory bank of said first group of said memory banks, resulting in one of said memory banks of said first group of memory banks being selected by an activation of the first respective bank selection signal;
and
a second memory bank decoder connected to a second group of said memory banks and having an axially mirror-symmetrical layout with respect to said first memory bank decoder, said second memory bank decoder having an input side, an output side and generating a second respective bank selection signal available at said output side for each memory bank of said second group of said memory banks, resulting in that one of said memory banks of said second group of said memory banks being selected by an activation of the second respective bank selection signal;
and
a predecoder having a logic circuit, an input side and an output side, said predecoder generating on said output side first address signals and second address signals complementary to the first address signals, the first address signals and the second address signals being fed to said first memory bank decoder and said second memory bank decoder, respectively, and said input side of said predecoder receiving a portion of the address bits.

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Dependencies are inferred from the claim text.

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Abstract

A semiconductor memory, comprising:

a number of memory banks, each including:
a memory cell array having a multiplicity of memory cells disposed in a matrix-like manner having rows and columns and defining a matrix of memory cells;
and
an address decoder for selecting one of a row and a column of said matrix of memory cells;
means for feeding in an address containing a number of address bits for selecting one of said row and said column of one of said memory cells by addressing said address decoder;
memory bank decoders, including:
a first memory bank decoder connected to a first group of said memory banks, said first memory bank decoder having an input side, an output side and generating a first respective bank selection signal available at said output side for each memory bank of said first group of said memory banks, resulting in one of said memory banks of said first group of memory banks being selected by an activation of the first respective bank selection signal;
and
a second memory bank decoder connected to a second group of said memory banks and having an axially mirror-symmetrical layout with respect to said first memory bank decoder, said second memory bank decoder having an input side, an output side and generating a second respective bank selection signal available at said output side for each memory bank of said second group of said memory banks, resulting in that one of said memory banks of said second group of said memory banks being selected by an activation of the second respective bank selection signal;
and
a predecoder having a logic circuit, an input side and an output side, said predecoder generating on said output side first address signals and second address signals complementary to the first address signals, the first address signals and the second address signals being fed to said first memory bank decoder and said second memory bank decoder, respectively, and said input side of said predecoder receiving a portion of the address bits.

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