Dual access memory array

Abstract

A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words. The dual access controller includes a multiple row main controller and a half row line decoder. The multiple row main controller receives the word address N and the word separation amount S and activates column and output multiplexers. It also determines the half row or rows on which the main and second words are found. The half row line decoder activates the half row or rows as indicated by the multiple row main controller.

Dependencies are inferred from the claim text.