Semiconductor memory device column select circuit and method for minimizing load to data input/output lines

A semiconductor memory device for selecting a bank among a plurality of banks sharing data input/output lines, the banks are arranged in rows and columns, and selecting a predetermined bit line among a plurality of bit lines in the selected bank, to transfer the data of the selected bit line to the data input/output lines, the semiconductor memory device comprising column select circuits arranged between the banks, each column select circuit shared by neighboring banks, for transferring data of the selected bit line to the data input/output lines, wherein each column select circuit comprises:

• a plurality of first select portions for connecting the bit lines of the selected bank to the corresponding first data lines in response to a bank select signal to select a predetermined bank;
• a plurality of second select portions for connecting the first data lines to a second data line in response to each column select signal which represents the address of each bit line;
• and
• a third select portion for connecting the second data line to the data input/output lines in response to the bank select signal.

An arrangement method for a semiconductor memory device for selecting a bank among at least two banks which share data input/output lines, the banks being arranged in units of memory blocks, and selecting a predetermined bit line among a plurality of bit lines in the selected bank, to transfer the data of the selected bit line to the data input/output lines, the method comprising:

• providing a bit line sense amplifier for sensing the data of the bit lines;
• providing a column select circuit for (i) connecting the bit lines of the selected bank to the corresponding first data lines through first select portions in response to a bank select signal to select a predetermined bank, (ii) connecting the first data lines to a second data line through second select portions in response to each column select signal which represents the address of each bit line, and (iii) connecting the second data line to the data input/output lines through a third select portion in response to the bank select signals,
• providing a sense amplifier power driver for supplying power voltage to the bit line sense amplifier;
• providing a data line equalizer for equalizing the second data line;
• and
• arranging the third select portion in the bit line sense amplifier region between the banks.

An arrangement method for a semiconductor memory device including banks each having separate global data input/output lines, and memory blocks in which a plurality of sub-blocks obtained by dividing a bank in rows and columns are arranged, the semiconductor memory device selecting one of the banks and selecting a predetermined bit line among a plurality of bit lines of the selected bank to transfer the data of the selected bit line to the global data input/output lines, the semiconductor memory device comprising:

• a bit line sense amplifier for sensing the data of the bit lines;
• switching portions for connecting local data lines to which the sensed bit line data is transferred to the global data input/output lines;
• and
• data line equalizers for equalizing the local data lines,
• wherein the switching portion is arranged in the bit line sense amplifier region among the sub-blocks.