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US 6,188,630 B1Granted
Semiconductor memory device
AssigneeOki Electric Industry Co., Ltd.
InventorsTakashi Ohno, Hitoshi Doi
Life of this patent
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Abstract
A semiconductor memory device includes first through fourth memory blocks. A first block-selection signal is used to select the first and third memory blocks, to output data from the first memory block to the first data line and also to output data from the fourth memory block to the second data line. A second block-selection signal is used to select the second and third memory blocks, to output data from the second memory block to the second data line and also to output data from the third memory block to the first data line.
Claims21
A semiconductor memory device comprising:
- a first pair of data lines and a second pair of data lines;
- a plurality of first and second column-selection signal lines for transferring a plurality of column-selection signals;
- a block selection signal line for transferring a block selection signal;
- a first memory block including
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of a pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which is connected to one of the first column-selection signal lines, one of the pairs of the bit lines and the first pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the first pair of data lines in response to the column selection signal, and
- a control circuit connected to said block selection signal line, the control circuit enabling said first memory block in response to the block selection signal;
- a second memory block including
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which is connected to one of the first column-selection signal lines, one of the pairs of the bit lines and the second pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the second pair of data lines in response to the column selection signal, and
- a control circuit connected to said block selection signal line, the control circuit enabling said second memory block in response to the block selection signal;
- a third memory block including
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which is connected to one of the second column-selection signal lines, one of the pairs of the bit lines and the first pair of data lines, the column switch circuit transferring data on the pairs of bit lines to the first pair of data lines in response to the column selection signal, and
- a control circuit connected to said block selection signal line, the control circuit enable said third memory block in response to the block selection signal;
- and
- a fourth memory block including
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which is connected to one of the second column-selection signal lines, one of the pairs of bit lines and the second pair of data lines, the column switch circuit transferring data on the pairs of it lines to the second pair of data lines in response to the column selection signal, and
- a control circuit connected to said block selection signal line, the control circuit enabling said fourth memory block in response to the block selection signal.
25 more elements
A semiconductor memory device comprising:
- a plurality of pairs of data lines including a first pair of data lines and a second pair of data lines;
- a plurality of column selection signal lines for transferring a plurality of column selection signals, said column selection signal lines including a plurality of first column selection signal lines and a plurality of second column selection signal lines;
- a block selection signal line for transferring a block selection signal line;
- and
- a plurality of memory blocks each of which includes
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which has a control terminal connected to one of the column selection signal lines, a first terminal connected to one of the pairs of the bit lines, the column switch circuit transferring data on the pair of bit lines, the column switch circuit transferring data on the pair of bit lines to the pair of data lines in response to the column selection signal, and
- a control circuit connected to said block selection signal line, the control circuit enabling the memory block in response to the block selection signal, said memory blocks including first, second, third and fourth memory blocks, and
- wherein each of the control terminals of the column switch circuits of the first and second memory blocks are commonly connected to one of the first column selection signal lines respectively, and each of the control terminals of the column switch circuits of the third and fourth memory blocks are commonly connected to one of the second column selection signal lines respectively, and
- wherein the second terminals of the column switch circuits of the first and third memory blocks are commonly connected to the first pair of data lines, and the second terminals of the column switch circuits of the second and fourth memory blocks are commonly connected to the second pair of data lines.
9 more elements
A semiconductor memory device comprising:
- a first pair of data lines;
- a second pair of data lines;
- a plurality of first column selection signal lines each of which transfers a first column selection signals;
- a plurality of second column selection signal lines each of which transfers a second column selection signal;
- and
- a plurality of memory blocks each of which includes
- a plurality of memory cells,
- a plurality of word lines connected to the memory cells,
- a plurality of pairs of bit lines, each of which is connected to the memory, cells,
- a plurality of column switch circuits each of which has a control terminal, a first terminal connected to one of the pairs of the bit lines and a second terminal, the column switch circuit transferring data on the pair of bit lines to the second terminal thereof in response to a signal received to the control terminal thereof, and
- a control circuit enabling the memory block in response to a signal received thereto, said memory blocks including first, second, third and fourth memory blocks, and
- wherein each of the control terminals of the column switch circuits of the first and second memory blocks are commonly connected to one of the first column selection signal lines respectively, and each of the control terminals of the column switch circuits of the third and fourth memory blocks are commonly connected to one of the second column selection signal lines respectively,
- wherein the second terminals of the column switch circuits of the first and third memory blocks are commonly connected to said first pair of data lines, and the second terminals of the column switch circuits of the second and fourth memory blocks are commonly connected to said second pair of data lines, and
- wherein the control circuits of the first and third memory blocks commonly receives a first block selection signal and the control circuits of the second and fourth memory blocks commonly receives a second block selection signal.
11 more elements
Dependencies are inferred from the claim text.