Low power, static content addressable memory
OwnerCecil H. Kaplinskyinventor
Life of this patent
Estimating the term…
Abstract
A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.
Claims11
A low power, static content addressable memory comprising:
- a plurality of memory cells, each memory cell having a set of complementary bit lines and including a first array of transistors for storing data and a second array of transistors for comparing a stored data item and a data item applied to the cell by the bit lines and producing a result on a selection line, the first array of transistors consisting of four storage transistors and two access transistors, the two access transistors being connected to the bit lines and to a word line. and the second array consisting of two transistors, as well as the two access transistors from the first array, in order to perform a comparison function;
- and
- a plurality of combinational logic gates having inputs provided from the selection lines of the memory cells and producing an output which is a full match line.
A low power, static, dual port, content addressable memory comprising:
- a plurality of memory cells, each memory cell having two or more sets of complementary bit lines and including a first array of transistors for storing data and a second array of transistors for comparing a stored data item and a data item applied to the cell by the bit lines and producing a result on a selection line, the first array of transistors consisting of four storage transistors and two sets of access transistors, each set of access transistors consisting of two access transistors, each access transistor being connected to one of the sets of bit lines and to a word line, and the second array consisting of two transistors, as well as the two sets of access transistors from the first array in order to perform a comparison function;
- and
- a plurality of combinatorial logic gates having inputs provided from the selection lines of the memory cells and producing an output which is a full match line.
A low power, static content addressable memory comprising:
- a plurality of memory cells, each memory cell having a set of complementary bit lines and including a first array of transistors for storing data and a second array of transistors for comparing a stored data item and a data item applied to the cell by the bit lines and producing a result on a selection line;
- a plurality of NAND gates, each NAND gate having inputs provided from the selection lines of the memory cells and producing an output;
- a plurality of NOR gates, each NOR gate having inputs provided from the outputs of the NAND gates and producing an output;
- and
- one or more AND gates having inputs provided from the outputs of the NOR gates, providing an output which is a full match line.
Dependencies are inferred from the claim text.