Low latency memory sensing circuits
AssigneeWinbond Electronics Corp.
InventorHua Zheng
Life of this patent
Estimating the term…
Abstract
Memory sensing circuits having low latency or delay. Low latency can be achieved, in part, by utilizing multiple amplifiers in the sense amplifier circuit. Each amplifier detects and amplifies a differential voltage on a pair of lines used for sensing a logic state of a memory cell. The use of multiple amplifiers improves the response times of the lines, which can allow for an earlier detection of the voltages on the lines, a shorter memory access cycle, and an improved data transfer rate. Low latency can also be achieved by using a set of isolation switches and a latch in the sense amplifier circuit. The latch “captures” the voltages on the lines after the voltages have exceeded a set of thresholds. The latch provides the captured value to subsequent circuitry at the same time that the lines are “deactivated.”
Claims31
A sense amplifier circuit for sensing a logic state of a memory cell comprising:
- an isolation circuit coupled between a first pair of lines and a second pair of lines, wherein the memory cell is operatively coupled to at least one of the lines in the second pair and shares charge, when selected, with the at least one coupled line;
- a first amplifier coupled between the first pair of lines, the first amplifier configured to detect and amplify a voltage difference between the first pair of lines;
- a second amplifier coupled between the first pair of lines, the second amplifier configured to detect and amplify the voltage difference between the first pair of lines;
- and
- a third amplifier coupled between the second pair of lines, the third amplifier configured to detect and amplify a voltage difference between the second pair of lines, and
- wherein the first, second, and third amplifiers are configured to provide amplification of a voltage generated by the memory cell and are enabled in a particular order to provide improved sensing time for the memory cell.
A sense amplifier circuit for sensing a logic state of a memory cell comprising:
- an isolation circuit coupled between a pair of sense amplifier lines and a pair of bit lines, wherein the memory cell is coupled to at least one of the bit lines and shares charge, when selected, with the at least one coupled line;
- a first amplifier coupled between the sense amplifier lines, the first amplifier configured to detect and amplify a differential voltage on the sense amplifier lines;
- a second amplifier coupled between the sense amplifier lines or the bit lines, the second amplifier configured to detect and amplify the differential voltage on the lines to which it couples;
- a first set of switches coupled between the pair of sense amplifier lines and a pair of intermediate signal lines;
- a latch coupled between the intermediate signal lines, the latch configured to latch a differential voltage on the intermediate signal lines;
- and
- a second set of switches coupled between the pair of intermediate signal lines and a pair of data lines.
A sense amplifier circuit for sensing a logic state of a memory cell comprising:
- an isolation circuit coupled between a pair of sense amplifier lines and a pair of bit lines, wherein the memory cell is coupled to at least one of the bit lines and shares charge, when selected, with the at least one coupled bit line;
- a N-channel amplifier coupled between the sense amplifier lines, the N-channel amplifier configured to detect and amplify a differential voltage on the sense amplifier lines;
- a P-channel amplifier coupled between the sense amplifier lines, the P-channel amplifier configured to detect and amplify the differential voltage on the sense amplifier lines;
- and
- an additional amplifier coupled between the bit lines, the additional amplifier configured to detect and amplify a differential voltage on the bit lines, and
- wherein the N-channel, P-channel, and additional amplifiers are configured to provide amplification of a voltage generated by the memory cell and are enabled in a particular order to provide improved sensing time for the memory cell.
A memory device comprising:
- a row decoder configured to receive address information and generate a first set of control signals;
- a column decoder configured to receive address information and generate a second set of control signals;
- a memory array coupled to the row and column decoders, the memory array configured to provide a data value in response to the first and second sets of control signals;
- and
- a sense amplifier coupled to the memory array, the sense amplifier configured to receive and sense the data value and provide a data bit, the sense amplifier including
- an isolation circuit coupled between a pair of sense amplifier lines and a pair of bit lines, wherein the data value is provided to at least one of the bit lines,
- a first amplifier coupled between the sense amplifier lines, the first amplifier configured to detect and amplify a differential voltage on the sense amplifier lines,
- a second amplifier coupled between the sense amplifier lines, the second amplifier configured to detect and amplify the differential voltage on the sense amplifier lines, and
- a third amplifier coupled between the bit lines, the third amplifier configured to detect and amplify a differential voltage on the bit lines, and
- wherein the first, second, and third amplifiers are configured to provide amplification of the differential voltage on the bit lines corresponding to the data value, and wherein the amplifiers are enabled in a particular order to provide improved sensing time for the data value.
Dependencies are inferred from the claim text.