Back to results
US 6,188,623 B1Granted
Voltage differential sensing circuit and methods of using same
AssigneeMicron Technology, Inc.
InventorChristopher K. Morzano
Life of this patent
Estimating the term…
Abstract
A voltage differential sensing circuit and methods of operation are disclosed for use in a memory device. The sensing circuit utilizes the inherent delay during sensing, i.e., the period between when an enable signal is enabled and when data is valid, by pulling a node of a transition logic circuit to a midpoint voltage. As the node of the transition logic circuit starts at a midpoint voltage, the voltage swing to valid data is faster because the output no longer needs to swing from rail to rail as before.
Claims16
A sensing circuit for sensing a voltage differential comprising:
- a helper flip-flop for receiving complementary data input signals from a voltage differential and an enable signal and outputting a first latched data signal and a second latched data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal, said first latched data signal and said second latched data signal, and generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data output circuit coupled to said transition logic circuit for receiving said first timing signal and said second timing signal and driving an output signal indicative of said voltage differential.
6 more elements
A random access memory circuit comprising:
- a memory array;
- and
- a sense amplifier coupled to said memory array, comprising:
- a sensing circuit, comprising:
- a helper flip-flop for receiving a pair of complementary data signals and an enable signal and outputting a first latched data signal and a second latched data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal and said first latched data signal and said second latched data signal and generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data output circuit coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal.
10 more elements
An electronic system comprising an input device, an output device, a memory device, and a processor device operably coupled to the input device, and output device, and memory device, wherein the memory device comprises:
- a memory controller;
- and
- at least one random access memory circuit coupled to the memory controller, the at least one random access memory circuit comprising:
- a memory array;
- a sensing circuit coupled to said memory array, comprising:
- a helper flip-flop for receiving a pair of complementary data signals and an enable signal and outputting a first latched data signal and a second latched data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal, said first latched data signal and said second latched data signal and generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data output circuit coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal.
11 more elements
A semiconductor substrate having at least one random access memory circuit fabricated thereon, the at least one random access memory circuit comprising:
- a memory array;
- and
- a sensing circuit coupled to said memory array, comprising:
- a helper flip-flop for receiving a pair of complementary data signals and an enable signal and outputting a first latched data signal and a second latched data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal said first latched data signal and said second latched data signal and generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data output circuit coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal.
9 more elements
A sensing circuit for use in a memory array, comprising:
- a pair of complementary data signal lines;
- an enable line;
- a helper flip-flop, coupled to said pair of complementary data signal lines and said enable line for outputting latched complementary data signal lines;
- a transition logic circuit coupled to said latched complementary data signal lines and said enable line for generating a first timing signal and outputting a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data driver circuit coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal.
8 more elements
A semiconductor wafer on which is fabricated at least one memory circuit, said at least one memory circuit comprising:
- a memory array;
- and
- a sensing circuit coupled to said memory array, comprising:
- a helper flip-flop for receiving a pair of complementary data signal lines and an enable line for outputting a first latched data signal and a second latched data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal said first latched data signal and said second latched data signal for generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate
- a second NAND gate;
- a third NAND gate;
- and
- an inverter, and
- a data output circuit coupled to said transition logic circuit for receiving said second timing signal and said third signal and for driving an output signal.
8 more elements
A sensing circuit for sensing a voltage differential comprising:
- a helper flip-flop for receiving complementary data input signals from a voltage differential and an enable signal and outputting a first latched complementary data signal and a second latched complementary data signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said enable signal and said first latched complementary data signal and said second latched complementary data signal, and generating a first timing signal, a second timing signal and a third timing signal, wherein said transition logic circuit drives said second timing signal and said third timing signal to the same logical state as the first latched complementary data signal when said enable signal is enabled and wherein said transition logic circuit includes a first NAND gate, a second NAND gate, a third NAND gate and an inverter;
- and
- a data driver coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal indicative of said voltage differential.
1 more element
A semiconductor device for driving an output signal to a logical state based on a voltage differential sensed between a pair of complementary data signals comprising:
- a helper flip-flop for receiving said pair of complementary data signals and an enable signal and outputting a sensed signal and a complementary sensed signal;
- a transition logic circuit coupled to said helper flip-flop for receiving said sensed signal and said complementary sensed signal and said enable signal and outputting a second timing signal and a third timing signal, wherein said transition logic circuit includes:
- a first NAND gate;
- a second NAND gate;
- a third NAND gate;
- and
- an inverter;
- and
- a data driver coupled to said transition logic circuit for receiving said second timing signal and said third timing signal and driving an output signal.
6 more elements
Dependencies are inferred from the claim text.