US 6,188,621 B1 · Test circuit for flash memory device and method thereof

Abstract

There is disclosed a test circuit for a flash memory device and method thereof, which comprises a byte program means for performing a byte program according to a byte program enable signal and a cell address signal and outputting the last address signal of a sector, a program fail signal and an address signal of the fail cell; a chip erase means for performing a chip erase operation according to an erase enable signal and said sector address signal and for outputting an erase fail signal and an address signal of a fail sector; a sector address increment means for increasing a sector address according to said sector address signal and outputting the last sector address signal; a first means for generating a test signal according to the test enable signal, said last sector address signal, a test erase enable signal, said program fail signal and said erase fail signal; a second means for generating a test program enable signal or a test erase enable signal according to the last sector address signal and the test signal to supply them to said byte program means or said chip erase means; and an address/sector decoder for decoding the address from an address pad into a cell address and a sector address to supply them said byte program means and said chip erase means, respectively.

Claims6

Dependent claims

A test circuit for a flash memory device, comprising:

a byte program means for performing a byte program according to a byte program enable signal and a cell address signal and outputting the last address signal of a sector, a program fail signal and an address signal of the fail cell;
a chip erase means for performing a chip erase operation according to an erase enable signal and said sector address signal and for outputting an erase fail signal and an address signal of a fail sector;
a sector address increment means for increasing a sector address according to said sector address signal and outputting the last sector address signal;
a first means for generating a test signal according to the test enable signal, said last sector address signal, a test erase enable signal, said program fail signal and said erase fail signal;
a second means for generating a test program enable signal or a test erase enable signal according to the last sector address signal and the test signal to supply them to said byte program means or said chip erase means;
and
an address/sector decoder for decoding the address from an address pad into a cell address and a sector address to supply them said byte program means and said chip erase means, respectively.

4 more elements

Dependencies are inferred from the claim text.

Test circuit for flash memory device and method thereof

Life of this patent

Test circuit for flash memory device and method thereof

Life of this patent

Abstract

Claims6