Semiconductor memory device having a redundancy judgment circuit
AssigneeNEC Corporation
InventorMasahiro Shibuya
Life of this patent
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Abstract
A semiconductor memory device includes a redundancy word driver to select a redundancy memory cell and a main word driver to select a normal memory cell, wherein it is judged on the basis of an address input whether a redundancy memory cell or a main word is selected and thereby, a time to drive a word line is shortened. In a redundancy judgment circuit, control signals RDC0 to activate redundancy word drivers and a control signal XDC to activate a main word driver are produced, by using dynamic NOR circuits and a dynamic AND circuit that can each set an initial state of an output signal thereof regardless of an input signal, wherein the control signals RDC and XDC in initial states are respectively set to levels at which the redundancy word drivers and main word driver are all inactive.
Claims13
A semiconductor memory device comprising:
- a plurality of normal memory cells;
- a plurality of redundancy memory cells provided for defect relief in the normal memory cells;
- a main word driver that drives a normal word line to select said plurality normal memory cells, when in an active state;
- a redundancy word driver that drives a redundancy word line to select said plurality of redundancy memory cells, when in an active state;
- and
- a redundancy judgment circuit that judges whether or not an address signal input is of a defect address in said plurality of normal memory cells and, when the address signal is of the defect address, places the redundancy word driver in the active state without placing the main word driver in the active state, while, when the address signal is not of the defect address, placing the main word driver in the active state without placing the redundancy word driver in the active state,
- wherein, said redundancy judgment circuit places both the redundancy word driver and the main word driver in the respective inactive states in an initial state before the address signal is input to the redundancy judgment circuit, and said main word driver is supplied with said address signal whether said address signal is said defect address or not.
A semiconductor memory device comprising main memory cells that are normally used and redundancy memory cells for defect relief in the main memory cells, including:
- a main word driver that receives a first control signal and, when the first control signal is at a first level, selects the main memory cell, while, when the first control signal is at a second level, not selecting the main memory cell;
- a redundancy word driver that receives said second control signal and, when the second control signal is at a first level, selects the redundancy memory cell, while, when said second control signal is at said second level, not selecting the redundancy memory cell;
- an address judgment circuit that when an address signal is input and address information shown by the address signal coincides with an address of the redundancy memory cell, outputs a judgment signal at said first level, while in no coincidence, outputting a judgment signal at said second level;
- and
- a redundancy judgment circuit that receives said judgment signal and, when the judgment signal is at said first level, sets said second control signal to said first level, while, when the judgment signal is at said second level, setting said second control signal to said second level,
- wherein before said redundancy judgment circuit receives the judgment signal from said address judgment circuit, said redundancy judgment circuit sets said first and second control signals to respective said second levels.
A semiconductor memory device comprising:
- a main word driver receiving an address signal and a main word select signal, and driving a main word line according to said address signal and said main word select signal;
- a redundancy word driver receiving a redundancy word select signal and driving a redundancy word line according to said redundancy word select signal;
- and
- a redundancy judgment circuit receiving a defect address judgment signal and a reset signal, and outputting said main word select signal and said redundancy word select signal;
- wherein said redundancy judgment circuit initializes said main word select signal and said redundancy word select signal to inactive states when said reset signal is in active state, activates said redundancy word select signal when said defect address judgment signal becomes active, and activates said main word select signal when said redundancy word select has kept in inactive state for a predetermined period.
Dependencies are inferred from the claim text.