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US 6,188,619 B1Granted
Memory device with address translation for skipping failed memory blocks
AssigneeSamsung Electronics Co., Ltd.
InventorSeong-ook Jung
Life of this patent
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Abstract
A semiconductor memory device capable of operating normally even when a failed memory cell remains after repair. The semiconductor memory device includes a plurality of memory cell array blocks, and address decoding circuitry for receiving an address and for accessing good memory cell array blocks and skipping failed memory cell array blocks.
Claims10
A semiconductor memory device comprising:
- a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective;
- address decoding circuitry for receiving an address;
- a selection signal generator for generating a selection signal indicating which blocks have good memory cells and which blocks have at least one bad memory cell;
- and
- a multiplexer responsive to the address decoding circuitry and the selection signal for generating an internal address for accessing memory cell array blocks having good memory cells and skipping memory cell array blocks having at least one defective memory cell.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective;
- address decoding circuitry for receiving and decoding a first address, decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address;
- a selection signal generator that generates a selection signal indicating which blocks have good memory cells and which blocks have at least one bad memory cell;
- and
- a multiplexer responsive to the first address and the selection signal for generating an internal address signal;
- wherein if the memory device has no memory cell array block having at least one defective memory cell, the internal address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is different from the first address.
3 more elements
A method for addressing a plurality of memory cell array blocks in a semiconductor memory device, said method comprising:
- determining which memory cell array blocks of the plurality of memory cell array blocks have at least one defective memory cell;
- receiving a first address providing for access to one of the memory cell array blocks;
- decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address;
- and
- generating a selection signal that indicates which memory cell array blocks have good memory cells and which memory cell array blocks have bad memory cells;
- multiplexing the first address and the selection signal to generate an internal address;
- wherein if the memory device has no memory cell array block having at least one defective memory cell, the internal address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is different from the first address.
4 more elements
Dependencies are inferred from the claim text.