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US 6,188,618 B1Granted
Semiconductor device with flexible redundancy system
AssigneeKabushiki Kaisha Toshiba
InventorSatoru Takase
Life of this patent
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Abstract
A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.
Claims25
A semiconductor storage device comprising:
- a memory cell array having memory cells arranged in columns and rows, the memory cell array being divided into a plurality of sub cell arrays;
- redundancy cell arrays each located adjacent to a corresponding one of the sub cell arrays;
- row decoders for each selecting a corresponding one of the rows of the memory cell array in accordance with a first input address;
- column decoders for each selecting a corresponding one of the columns of the memory cell array in accordance with a second input address;
- a plurality of storage circuits each for storing an address assigned to a defective memory cell included in the memory cell array, and also storing mapping information indicative of the relationship with the redundancy cell arrays, the storage circuits outputting, when an address assigned to one of the defective memory cells stored therein matches the second input address, a replacement control signal for the defective memory cell on the basis of the result of matching, and the mapping information;
- and
- spare decoders each to be activated by the replacement control signal supplied from the storage circuits to thereby select a corresponding one of the redundancy cell arrays, and
- wherein the number of the storage circuits is smaller than the number of the redundant cell arrays.
5 more elements
A semiconductor storage device comprising:
- a memory cell array having memory cells arranged in columns and rows, the memory cell array being divided into a plurality of sub cell arrays;
- redundancy cell arrays each located adjacent to a corresponding one of the sub cell arrays;
- row decoders for each selecting a corresponding one of the rows of the memory cell array in accordance with a first input address;
- column decoders for each selecting a corresponding one of the columns of the memory cell array in accordance with a second input address;
- a plurality of storage circuits each including:
- a plurality of first storage elements for storing addresses assigned to defective memory cells included in the memory cell array;
- a plurality of second storage elements for storing mapping information which indicates the relationship with the redundancy units;
- a plurality of comparators each for comparing the address of a corresponding one of the defective memory cells stored in a corresponding one of the first storage elements with the second input address, and outputting, when the stored address matches the second input address, a signal indicating that those addresses match each other;
- and
- a decoder for decoding the mapping information stored in the second storage elements when each of the comparators output the signal indicating that the addresses match each other;
- and
- spare decoders each to be activated by the output signal of the decoder to thereby select a corresponding one of the redundancy cell arrays.
9 more elements
A semiconductor storage device comprising:
- a memory cell array having memory cells arranged in columns and rows;
- a plurality of redundancy cell arrays provided in the memory cell array;
- and
- a plurality of storage circuits each for storing an address assigned to a defective memory cell included in the memory cell array, and also storing mapping information indicative of the relationship with the redundancy cell arrays, the storage circuits outputting, when an address assigned to one of the defective memory cells stored therein matches an input address, a replacement control signal for the defective memory cell on the basis of the mapping information, and
- wherein the number of the storage circuits is smaller than the number of the redundant cell arrays.
2 more elements
Dependencies are inferred from the claim text.