Semiconductor memory device having a compensating write pulse width in response to power supply voltage

A write pulse width compensating circuit, comprising:

• a write enable delay circuit that receives a write enable signal and outputs a delayed write enable signal;
• a voltage sensing circuit that determines a power supply voltage and outputs a delay selection signal;
• and
• a generating circuit that receives the delayed write enable signal, the write enable signal and the delay selection signal and produces a write control drive signal based on the power supply voltage, wherein a transition edge of the write enable signal transits at a different point of time from a transition edge of the write control drive signal when the delay selection signal indicates the power supply voltage to be a first prescribed level, and the transition edge of the write enable signal transits substantially at a same time as the transition edge of the write control drive signal when the delay selection signal indicates the power supply voltage to be a second prescribed level.

A semiconductor device, comprising:

• a write pulse width compensating circuit that compensates a write control drive signal based on a power supply voltage;
• a first generating circuit that receives the write control drive signal, a first selection signal and a second selection signal and outputs a control signal for a selected cell;
• and
• a data input circuit that receives data and writes the data to the selected cell based on application of the data and the control signal, wherein said write pulse width compensating circuit includes a voltage sensing circuit that senses the power supply voltage and said voltage sensing circuit includes
• first, second, third and fourth transistors coupled in series to the power supply voltage,
• a first logic circuit that logically processes a chip enable signal,
• a fifth transistor having a control electrode that receives an output signal of the first logic circuit and a second electrode that receives the power supply voltage,
• a sixth transistor having a second electrode coupled to a first electrode of the fifth transistor and a control electrode that receives an output signal of the fourth transistor,
• a seventh transistor coupled in series with the sixth transistor with a control electrode that receives the output signal of the fourth transistor, and
• an eighth transistor coupled in series to the seventh transistor having a first electrode coupled to a ground voltage and a control electrode that receives the chip enable signal.

A write pulse width compensating circuit, comprising:

• a write enable delay circuit that receives a write enable signal and outputs a delayed write enable signal;
• a voltage sensing circuit that determines a power supply voltage and outputs a delay selection signal;
• and
• a generating circuit that receives the delayed write enable signal, the write enable signal and the delay selection signal and produces a write control drive signal based on the power supply voltage, wherein the voltage sensing circuit includes
• first, second, third and fourth transistors coupled in series to the power supply voltage,
• a first logic gate that logically processes a chip enable signal,
• a fifth transistor having a control electrode that receives an output signal of the first logic gate and a second electrode that receives the power supply voltage,
• a sixth transistor having a second electrode coupled to a first electrode of the fifth transistor and a control electrode that receives an output signal of the fourth transistor,
• a seventh transistor coupled in series with the sixth transistor with a control electrode that receives the output signal of the fourth transistor, and
• an eighth transistor coupled in series to the seventh transistor having a first electrode coupled to a ground voltage and a control electrode that receives the chip enable signal.

A semiconductor device, comprising:

• a write pulse width compensating circuit that compensates a write control drive signal based on a power supply voltage;
• a first generating circuit that receives the write control drive signal, a first selection signal and a second selection signal and outputs a control signal for a selected cell;
• and
• a data input circuit that receives data and writes the data to the selected cell based on application of the data and the control signal, wherein said write pulse width compensating circuit includes
• a write enable delay circuit that receives a write enable signal and outputs a delayed write enable signal,
• a voltage sensing circuit that senses the power supply voltage and outputs a delay selection signal, and
• a second generating circuit that receives the delayed write enable signal, the write enable signal and the delay selection signal and produces the write control drive signal, and wherein the second generating circuit includes
• a first transistor with a control electrode receiving a chip enable signal and a second electrode coupled to the power supply voltage,
• a transfer gate enabled by an output signal of the voltage sensing circuit,
• an second transistor with a control electrode that receives the power supply voltage and a first electrode coupled to a ground voltage,
• a first logic gate that logically processes the write enable signal and an output signal of the transfer gate, wherein the output signal of the transfer gate is regulated by the second transistor,
• a delay circuit coupled in series to an output terminal of the first logic-gate to delay an output signal of the first logic-gate, and
• a second logic-gate that logically processes an output signal of the first logic-gate and an output signal of the delay circuit to output the write control drive signal.

A write pulse width compensating circuit, comprising:

• a write enable delay circuit that receives a write enable signal and outputs a delayed write enable signal;
• a voltage sensing circuit that determines a power supply voltage and outputs a delay selection signal;
• and
• a generating circuit that receives the delayed write enable signal, the write enable signal and the delay selection signal and produces a write control drive signal based on the power supply voltage, wherein the generating circuit includes
• a first transistor with a control electrode receiving a chip enable signal and a second electrode coupled to the power supply voltage,
• a transfer gate enabled by an output signal of the voltage sensing circuit,
• an second transistor with a control electrode that receives the power supply voltage and a first electrode coupled to a ground voltage,
• a first logic gate that logically processes the write enable signal and an output signal of the transfer gate, wherein the output signal of the transfer gate is regulated by the second transistor,
• a delay circuit coupled in series to an output terminal of the first logic-gate to delay an output signal of the first logic-gate, and
• a second logic-gate that logicallyprocesses an output signal of the first logic-gate and an output signal of the delay circuit to output the write control drive signal.