MRAM device including digital sense amplifiers
AssigneeHewlett-Packard Company
InventorsFrederick A. Perner, Kenneth J. Eldredge, Lung T. Tran
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Abstract
Resistance of a selected memory cell in a Magnetic Random Access Memory (“MRAM”) device is sensed by a read circuit including a direct injection charge amplifier, an integrator capacitor and a digital sense amplifier. The direct injection charge amplifier supplies current to the integrator capacitor while maintaining an equipotential voltage on non-selected memory cells in the MRAM device. As the direct injection charge amplifier applies a fixed voltage to the selected memory cell, the sense amplifier measures integration time of a signal on the integrator. The signal integration time indicates whether the memory cell MRAM resistance is at a first state (R) or a second state (R+ΔR).
Claims24
A method of sensing a resistance state of a selected memory cell in an MRAM device, the method comprising the steps of:
- using the selected memory cell and a supply voltage to charge an integrator;
- measuring an amount of time for a voltage on the integrator to reach a reference voltage;
- and
- comparing the amount of time to a threshold;
- whereby the selected memory cell is at a first resistance state if the amount of time is less than the threshold;
- and
- whereby the selected memory cell is at a second resistance state if the amount of time is greater than the threshold.
A circuit for sensing a resistance state of a memory cell in an MRAM device, the circuit comprising:
- an integrator;
- and
- a sense amplifier, coupled to the integrator and the memory cell, for measuring an amount of time for a voltage on the integrator to reach a reference voltage and for comparing the measured amount of time to a threshold;
- whereby the memory cell is at a first resistance state if the amount of time is less than the threshold;
- and
- whereby the memory cell is at a second resistance state if the amount of time is greater than the threshold.
An MRAM device comprising:
- an array of memory cells;
- and
- a read circuit for sensing resistance states of selected memory cells in the array, the read circuit including:
- means for applying a potential to a selected memory cell and an equal potential to unselected memory cells in the array during a read operation;
- means for integrating a current flowing through the selected memory cell during the read operation;
- means for measuring an amount of time for a voltage on the integrating means to reach a reference voltage;
- and
- means for comparing the measured amount of time to a threshold, the comparing means indicating a first resistance state of the selected memory cell when the amount of time is less than the threshold, the comparing means indicating a second resistance state of the selected memory cell when the amount of time is greater than the threshold.
A presettable counter for a sense amplifier of a read circuit of an MRAM device, the sense amplifier including a clock, the MRAM device having an I/O pad, the counter comprising:
- a plurality of registers, each register including a T-type flip-flop, each flip-flop having a clock input and a Q output, one of the registers providing a least significant bit, another one of the registers providing a most significant bit;
- the clock input of flip-flop of the least significant bit being coupled to an output of the clock, the Q output of each flip-flop being coupled to the clock input of a next higher flip-flop, except for the most significant bit;
- the Q output of the flip-flop of the most significant bit being coupled to the I/O pad.
Dependencies are inferred from the claim text.