Device and method in a semiconductor memory for erasing/programming memory cells using erase/program speeds stored for each cell

A semiconductor device comprising:

• logic circuitry;
• and
• an embedded memory coupled to the logic circuitry, the embedded memory including:
• a plurality of memory cells;
• a plurality of query cells, each associated with one of the memory cells for storing a value representative of a characteristic rate of change in the state of the associated memory cell;
• querying circuitry coupled to the query cells for retrieving the values stored therein;
• and
• state change circuitry coupled to the memory cells and the querying circuitry for changing the states of the memory cells in accordance with the values retrieved from their associated query cells.

A multi-bit per cell memory device comprising:

• a plurality of multi-bit memory cells;
• a plurality of query cells, each associated with one of the multi-bit memory cells for storing a value representative of a characteristic rate of change in the state of the associated multi-bit memory cell;
• querying circuitry coupled to the query cells for retrieving the values stored therein;
• and
• state change circuitry coupled to the multi-bit memory cells and the querying circuitry for changing the states of the multi-bit memory cells in accordance with the values retrieved from the respective query cells associated with the multi-bit memory cells.

A memory device comprising:

• a plurality of memory cells;
• a plurality of query cells, each associated with one of the memory cells for storing a value representative of a characteristic rate of change in the state of the associated memory cell;
• querying circuitry coupled to the query cells for retrieving the values stored therein;
• and
• state change circuitry coupled to the memory cells and the querying circuitry for changing the states of the memory cells in accordance with the values retrieved from the respective query cells associated with the memory cells.

A flash memory comprising:

• a plurality of flash memory cells;
• a plurality of flash query cells, each associated with one of the flash memory cells for storing a value representative of a characteristic rate of change in the state of the associated flash memory cell;
• querying circuitry coupled to the query cells for retrieving the values stored therein;
• and
• state change circuitry coupled to the flash memory cells and the querying circuitry for changing the states of the flash memory cells in accordance with the values retrieved from the respective query cells associated with the flash memory cells.

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, processor, and memory devices including a system for changing the state of a memory cell, the system comprising:

• a query cell for storing a value representative of a characteristic rate of change in the state of the memory cell;
• querying circuitry coupled to the query cell for retrieving the value stored therein;
• and
• state change circuitry coupled to the querying circuitry for changing the state of the memory cell in accordance with the value retrieved from the query cell.

A semiconductor substrate having a surface on which a system for changing the state of a memory cell is fabricated, the system comprising:

• a query cell for storing a value representative of a characteristic rate of change in the state of the memory cell;
• querying circuitry coupled to the query cell for retrieving the value stored therein;
• and
• state change circuitry coupled to the querying circuitry for changing the state of the memory cell in accordance with the value retrieved from the query cell.

A method of erasing a memory cell, the method comprising:

• storing a value representative of a characteristic rate of erasure of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• reading the state of the memory cell;
• and
• erasing the memory cell in accordance with the state thereof and the value retrieved from the query cell.

A method of programming a memory cell with a selected data bit, the method comprising:

• storing a value representative of a characteristic rate of programming of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• and
• programming the memory cell in accordance with the selected data bit and the value retrieved from the query cell.

A method of erasing a memory cell, the method consisting essentially of:

• storing a value representative of a characteristic rate of erasure of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• reading the state of the memory cell;
• and
• erasing the memory cell in accordance with the state thereof and the value retrieved from the query cell.

A method of programming a memory cell with a selected data bit, the method consisting essentially of:

• storing a value representative of a characteristic rate of programming of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• and
• programming the memory cell in accordance with the selected data bit and the value retrieved from the query cell.

A method of changing the state of a memory cell from a current state to a desired state representative of one or more data bits awaiting storage in the memory cell, the method comprising:

• storing a value representative of a characteristic rate of change in the state of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• reading the current state of the memory cell;
• and
• changing the state of the memory cell in accordance with the value retrieved from the query cell, the current state of the memory cell, and the desired state of the memory cell so the memory cell stores the one or more data bits awaiting storage therein.

A method of changing the state of a memory cell from a current state to a desired state without an interim erased state, the method comprising:

• storing a value representative of a characteristic rate of change in the state of the memory cell in a query cell associated with the memory cell;
• retrieving the value stored in the query cell;
• reading the current state of the memory cell;
• and
• changing the state of the memory cell from the current state to the desired state in accordance with the value retrieved from the query cell, the current state of the memory cell read therefrom, and the desired state of the memory cell without an interim erased state.

A system for changing the state of a memory cell, the system comprising:

• a flash cell for storing a value representative of a characteristic rate of change in the state of the memory cell;
• querying circuitry coupled to the query cell for retrieving the value stored therein;
• and
• state change circuitry coupled to the querying circuitry for changing the state of the memory cell in accordance with the value retrieved from the query cell.