Semiconductor memory

Abstract

A semiconductor memory includes: a plurality of memory cell transistors: a plurality of first bit lines; a plurality of second bit lines; a first transistor provided between a charging section for charging at least one of the plurality of first bit lines and the plurality of memory cell transistors; and a second transistor provided between a discharging section for discharging at least one of the plurality of second bit lines and the plurality of memory cell transistors, wherein one of a source region and a drain region of each of the plurality of memory cell transistors is formed as a part of one of the plurality of first bit lines, and the other of a source region and a drain region is formed as a part of one of the plurality of second bit lines; an ON/OFF state of the first transistor is controlled based on a first signal; an ON/OFF state of the second transistor is controlled based on a second signal; and the second signal is provided to the second transistor at a time which is delayed for a predetermined period from a time that the first signal is provided to the first transistor.

Dependencies are inferred from the claim text.