Back to results
US 6,188,609 B1Granted
Ramped or stepped gate channel erase for flash memory application
AssigneeAdvanced Micro Devices, Inc.
InventorsRavi S. Sunkavalli, Sameer S. Haddad
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeAdvanced Micro Devices, Inc.
InventorsRavi S. Sunkavalli, Sameer S. Haddad
Estimating the term…
A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.
A method for erasing a flash Electrically-Erasable Programmable Read Only Memory (EEPROM) that includes a plurality of field effect transistor memory cells each having a source, a drain, a floating gate, a well and a control gate, the method comprising the steps of:
Dependencies are inferred from the claim text.