Integrated circuit memory having divided-well architecture
AssigneeLucent Technologies Inc.
InventorChun Chen
Life of this patent
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Abstract
An integrated circuit has a memory array comprising memory devices formed in a multiplicity of electrically isolated semiconductor regions that share a common set of bit lines. A given semiconductor region, typically a tub, is biased to a given voltage if a memory cell formed in that tub is accessed for a write operation, and biased to another voltage at other times. Although there may be many memory devices along the same bit line, during programming only the memory devices in the selected tub will be disturbed by the tub bias. Other memory devices residing in unselected tubs are protected against the bit line disturb. The present technique is especially advantageous when used with flash EEPROM memory cells that utilize secondary electron injection to assist in programming the cells.
Claims4
An integrated circuit comprising:
- memory cells arranged in rows accessed by word lines and columns accessed by bit lines;
- a first group of said memory cells formed in a first semiconductor region, and a second group of memory cells formed in a second semiconductor region that is electrically isolated from said first semiconductor region, wherein said bit lines run between said first group and said second group,
- and wherein a selected one of said first and second semiconductor regions is biased by a given voltage when a cell in a group formed in said selected region is accessed for a write operation, and biased at a voltage different than said given voltage when no cell in said selected region is accessed for a write operation;
- and
- a multiplexer that selectively connects a source of said given voltage to a selected one of said first and said second semiconductor regions.
Dependencies are inferred from the claim text.