Non-volatile semiconductor memory using split bit lines

A non-volatile semiconductor memory comprising:

• a memory cell array including a plurality of non-volatile memory cells, and connected to a plurality of word lines and a plurality of bit lines, respectively;
• a row decoder for selecting said word lines on the basis of row address data;
• and
• a column decoder for selecting said bit lines on the basis of column address data;
• wherein
• said bit lines include a plurality of main bit lines connected to said column decoder and a plurality of split bit lines each connected to each of said plurality of main bit lines through each of a plurality of select transistors to determine which of the split bit lines is to be selected;
• and
• the split bit lines connected to a first main bit line and a second main bit line arranged adjacently thereto are arranged alternately adjacent to each other,
• wherein two split bit lines are connected to each of said main bit lines,
• wherein said main bit lines are electrode wirings interlayer-insulated from said split bit lines,
• a convex portion which partially protrudes from one side of each said electrode wirings is arranged at an area to which said select transistor is to be connected;
• and
• the convex portion of one main bit line is opposite to that of another main bit line adjacent thereto.

A non-volatile semiconductor memory comprising:

• a memory cell array including a plurality of non-volatile memory cells, and connected to a plurality of word lines and a plurality of bit lines, respectively;
• a row decoder for selecting said word lines on the basis of row address data;
• and
• a column decoder for selecting said bit lines on the basis of column address data;
• wherein
• said bit lines include a plurality of main bit lines connected to said column decoder and a plurality of split bit lines each connected to each of said plurality of main bit lines through each of a plurality of select transistors to determine which of the split bit lines is to be selected;
• and
• the split bit lines connected to a first main bit line and a second main bit line arranged adjacently thereto are arranged alternately adjacent to each other,
• wherein two split bit lines are connected to each of said main bit lines,
• wherein said plurality of unit patterns are arranged on a semiconductor substrate surface, and each said plurality of unit patterns comprises:
• a memory cell array block including split-type memory cells arranged in a matrix;
• select transistors arranged on both sides of each said memory cell array blocks in their arranging direction;
• discharge transistors arranged outside the select transistors;
• and
• three pairs of electrode wirings travelling in parallel to a direction of arranging the memory cells outside the discharge transistors.